a42mx02-2pq100m Actel Corporation, a42mx02-2pq100m Datasheet - Page 47

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a42mx02-2pq100m

Manufacturer Part Number
a42mx02-2pq100m
Description
40mx And 42mx Fpga Families
Manufacturer
Actel Corporation
Datasheet
Table 29 •
Parameter Description
CMOS Output Module Timing
t
t
t
t
t
t
d
d
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
4. Delays based on 35 pF loading.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
TLH
THL
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
CC
0.03
11.1
0.05
5.5
4.8
4.7
6.8
8.2
= 3.0V, T
v6.0
‘–2’ Speed
J
= 70°C)
0.05
0.03
12.8
5.5
7.9
9.5
6.4
5.5
‘–1’ Speed
14.5
10.7
0.06
0.04
7.2
6.2
6.2
8.9
‘Std’ Speed
40MX and 42MX FPGA Families
10.5
17.1
12.6
0.07
0.04
8.5
7.3
7.3
‘–F’ Speed
11.9
10.2
10.2
14.7
23.9
17.7
0.10
0.06
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
1-41

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