zl2005 Intersil Corporation, zl2005 Datasheet - Page 15

• Manufacturer Part Number: zl2005
• Description: Digital-dc? Integrated Power Management And Conversion Ic
• Manufacturer: Intersil Corporation

5
5.1 Internal Bias Regulators and Input
The ZL2005 employs two internal low dropout (LDO)
regulators to supply bias voltages for internal circuitry,
allowing it to operate from a single input supply. The
internal bias regulators are as follows:
VR: The VR LDO provides a regulated 5V bias supply
V25: The V25 LDO provides a regulated 2.5V bias
Note: The internal bias regulators are designed for
powering internal circuitry only. Do not attach exter-
nal loads to any of these pins. The multi-mode pins
may be connected to the VR or V25 pins for logic
HIGH settings.
When the input supply (VDD) is higher than 5.5V, the
VR pin should not be connected to any other pin. It
should only have a filter capacitor attached as shown
in Figure 9. Due to the dropout voltage associated with
the VR bias regulator, the VDD pin must be connected
to the VR pin for designs operating from a VDD sup-
ply from 3.0V to 5.5V. Figure 9 illustrates the required
connections for both cases. For input supplies between
4.5V and 5.5V, either method can be used.
for the MOSFET driver circuits. It is powered
from the VDD pin and can supply up to 100mA
output current. A 4.7 µF filter capacitor is
required at the VR pin.
supply for the main controller circuitry. It is
powered from an internal 5V node and can sup-
ply up to 50 mA output current. A 10 µF filter
capacitor is required at the V25 pin.
Figure 9. Input Supply Connections
Power Conversion Functional Description
Supply Connections
15
ZL2005
5.2 High-side Driver Boost Circuit
The gate drive voltage for the upper MOSFET driver
is generated by a floating bootstrap capacitor, CB (see
Figure 4). When the lower MOSFET (QL) is turned
on, the SW node is pulled to ground and the capacitor
is charged from the internal VR bias regulator through
diode DB. When QL turns off and the upper MOSFET
(QH) turns on, the SW node is pulled up to V
the voltage on the BST pin is boosted approximately
5V above V
high-side driver. A Schottky diode should be used for
DB to maximize the high-side drive voltage.
5.3 Output Voltage Selection
The output voltage may be set to any voltage between
0.6V and 5.5V provided that the input voltage is
higher than the desired output voltage by an amount
sufficient to prevent the device from exceeding its
maximum duty cycle specification. By connecting the
V0 and V1 pins to logic high, logic low, or leaving
them floating, V
voltages as shown in Table 6.
Table 6.
If an output voltage other than those in Table 6 is
desired, the resistor setting method can be used. Using
this method, resistors R0 and R1 are selected to pro-
duce a specific voltage between 0.6V and 5.5V in 10
mV steps. Resistor R1 provides a coarse setting and
R0 a fine adjustment, thus eliminating the additional
errors associated with using two 1% resistors in a stan-
dard analog implementation (this typically adds 1.4%
error using two 1% resistors).
V1
OPEN
HIGH
LOW
Pin-strap Output Voltage Settings
IN
to provide the necessary voltage for the
OUT
LOW
0.6V
1.2V
2.5V
can be set to any of nine standard
OPEN
0.8V
1.5V
3.3V
V0
February 18, 2009
HIGH
1.0V
1.8V
5.0V
DD
FN6848.0
and