zl2005 Intersil Corporation, zl2005 Datasheet - Page 18

• Manufacturer Part Number: zl2005
• Description: Digital-dc? Integrated Power Management And Conversion Ic
• Manufacturer: Intersil Corporation

Table 11. DLY and SS Resistor Values
The soft start delay and ramp period can be set to cus-
tom values via the I
soft start delay is set to 0 ms, the device will begin its
ramp up after the internal circuitry has initialized
(approx. 6ms).
100 ms
DLY or
10 ms
20 ms
30 ms
40 ms
50 ms
60 ms
70 ms
80 ms
90 ms
0 ms
SS
Figure 11. DLY and SS Pin Resistor
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
R
10 kΩ
11 kΩ
DLY
R
SS
Connections
or
2
N/C
ZL2005
C/SMBus interface. When the
R
SS
18
R
N/C
DLY
120 ms
130 ms
140 ms
150 ms
160 ms
170 ms
180 ms
190 ms
200 ms
DLY or
110 ms
SS
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
R
DLY
R
SS
or
ZL2005
5.6 Power Good
The ZL2005 provides a Power Good (PG) signal that
indicates the output voltage is within a specified toler-
ance of its target level and no fault condition exists. By
default, the PG pin will assert if the output is within -
10%/+15% of the target voltage These limits may be
changed via the I
Note AN13 for details.
A PG delay period is defined as the time from when all
conditions within the ZL2005 for asserting PG are met
to when the PG pin is actually asserted. This feature is
commonly used instead of using an external reset con-
troller to control external digital logic. By default, the
ZL2005 PG delay is set equal to the soft-start ramp
time setting. Therefore, if the soft-start ramp time is
set to 10 ms, the PG delay will be set to 10 ms. The PG
delay may be set independently of the soft-start ramp
using the I
AN13.
5.7 Switching Frequency and PLL
The ZL2005 incorporates an internal phase locked
loop (PLL) to clock the internal circuitry. The PLL can
be driven by an internal oscillator or driven from an
external clock source connected to the SYNC pin.
When using the internal oscillator, the SYNC pin can
be configured as a clock output for use by other
devices. The SYNC pin is a unique pin that can per-
form multiple functions depending on how it is config-
ured. The CFG pin is used to select the operating mode
of the SYNC pin as shown in Table 12. Figure 12
illustrates the typical connections for each mode.
Table 12. SYNC Pin Function Selection
CFG Pin
OPEN
HIGH
LOW
2
C/SMBus as described in Application Note
SYNC is configured as an input
Auto Detect mode
SYNC is configured as an output
f
SW
2
C/SMBus interface. See Application
= 400 kHz (default)
SYNC Pin Function
February 18, 2009
FN6848.0