ht82m9aae Holtek Semiconductor Inc., ht82m9aae Datasheet - Page 23

• Manufacturer Part Number: ht82m9aae
• Description: Usb Mouse Encoder 8-bit Mcu With Eeprom
• Manufacturer: Holtek Semiconductor Inc.

The MISC register is actually a command + status to control the desired FIFO action and to show the status of the de-
sired FIFO. Every bit¢s meaning and usage are listed as follows:
The HT82M9AEE/HT82M9AAE have two 8´8
bidirectional FIFO for the three endpoints (control and
Interrupt). User can easily read/write the FIFO data by
accessing the corresponding FIFO pointer register
(FIFO0, FIFO1, FIFO2). The following are two examples
for reading and writing the FIFO data:
HT82M9AEE/HT82M9AAE FIFO is read by packet. To
read from FIFO, the following should be followed:
·
·
·
·
·
·
User reads the data through the FIFO pointer register,
user has to record the number of bytes to be read. The
Rev. 1.20
Select one set of FIFO, set in the read mode (MISC
TX bit = 0), and set the REQ bit to ²1².
Check the ready bit until the status = 1
Read through the FIFO pointer register, and record
the data number that has been read.
Repeat steps 2 and 3 until the ready bit becomes 0
which indicates the end of the FIFO data reading.
Set MISC TX bit = 1
Clear the REQ bit to 0. Complete reading.
Sel_pipe1
Sel_pipe0
Function
Set CMD
Request
Ready
Name
Clear
Len0
Tx
Bit No.
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
After setting the other desired status, FIFO can be requested by setting this bit high ac-
tive. After work has been done, this bit must be set low.
Represents the direction and transition end of the MCU accesses. When being set as
logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be
set to logic 0 before terminating the request to represent a transition end. For reading
action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be
set to logic 1 after work is done.
Represents MCU clear requested FIFO, even if FIFO is not ready.
Determines which FIFO is desired, ²00² for FIFO 0, ²01² for FIFO 1 and ²10² for FIFO 2
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware.
So, even if the MCU is busy, nothing is missed by the SETUP command from the host.
Indicates that the desired FIFO is ready to work.
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
Sel_pipe1
Sel_pipe0
Function
Set CMD
Request
Ready
Clear
Len0
Tx
MISC (46H) Registers Table
MISC Function Table
23
HT82M9AEE/HT82M9AAE allows a maximum of 8
bytes of data in each packet.
The HT82M9AEE/HT82M9AAE FIFO is written by
packet. To write to FIFO, the following should be fol-
lowed:
·
·
·
·
·
·
User writes the data through the FIFO pointer register,
user has to record the number of bytes that have been
written. The HT82M9AEE/HT82M9AAE allows a maxi-
mum of 8 bytes of data in each packet.
Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to ²1²
Check the ready bit until the status = 1
Write through the FIFO pointer register and take down
the data number that has been written
Repeat steps 2 and 3 until writing is complete or the
ready bit becomes 0 which indicates that the FIFO no
longer allows any data writing.
Set MISC TX bit = 0
Clear the REQ bit to 0. Complete writing.
Description
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
HT82M9AEE/HT82M9AAE
Register Address
01000110B
August 13, 2007