gal20xv10 Lattice Semiconductor Corp., gal20xv10 Datasheet - Page 12

• Manufacturer Part Number: gal20xv10
• Description: High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

An electronic signature word is provided in every GAL20XV10
device. It contains 40 bits of reprogrammable memory that con-
tains user defined data. Some uses include user ID codes, revi-
sion numbers, pattern identification or inventory control codes. The
signature data is always available to the user independent of the
state of the security cell.
NOTE: The electronic signature bits, if programmed to any value
other then zero(0) will alter the checksum of the device.
A security cell is provided in every GAL20XV10 device as a deter-
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogram-
ming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able regardless of the security cell state.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes less than a
second. Erasing of the device is transparent to the user, and is done
automatically as part of the programming cycle.
Circuitry within the GAL20XV10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
Electronic Signature
Security Cell
Device Programming
Power-Up Reset
t
pr, 1 s MAX). As a result, the state
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
Q - OUTPUT
CLK
Vcc
Vcc (min.)
12
of system power-up, some conditions must be met to provide a valid
power-up reset of the GAL20XV10. First, the V
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
GAL20XV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
GAL20XV10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
GAL20XV10 input buffers have active pull-ups within their input
structure. This pull-up will cause any un-terminated input or
I/O to float to a TTL high (logical 1). Lattice Semiconductor
recommends that all unused inputs and tri-stated I/O pins be
connected to another active input, Vcc, or GND. Doing this will tend
to improve noise immunity and reduce Icc for the device.
t
pr
Latch-Up Protection
Input Buffers
Specifications GAL20XV10
Internal Register
Reset to Logic "0"
-20
-40
-60
Device Pin
Reset to Logic "1"
t
0
wl
t
su
0
Typical Input Pull-up Characteristic
t
1.0
pr time. As in normal system operation, avoid
Input Voltage (Volts)
2.0
3.0
4.0
CC
rise must be
5.0