adf7023-j Analog Devices, Inc., adf7023-j Datasheet - Page 51
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adf7023-j
Manufacturer Part Number
adf7023-j
Description
High Performance, Low Power, Ism Band Fsk/gfsk/msk/gmsk Transceiver Ic
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADF7023-J.pdf
(100 pages)
MEMORY ACCESS
Memory locations are accessed by invoking the relevant SPI
command. An 11-bit address is used to identify registers or
locations in the memory space. The most significant three bits
of the address are incorporated into the SPI command by
appending them as the LSBs of the command word. Figure 64
illustrates command, address, and data partitioning. The various
SPI memory access commands are different, depending on the
memory location being accessed (see Table 27).
An SPI command should be issued only if the SPI_READY bit
in the INTERRUPT_SOURCE_1 register (Address 0x337) of
the status word bit is high. The ADF7023-J interrupt handler
can also be configured to generate an interrupt signal on
IRQ_GP3 when the SPI_READY bit is high.
An SPI command should not be issued while the communications
processor is initializing (FW_STATE = 0x0F). SPI commands
can be issued in any other communications processor state,
including the busy state (FW_STATE = 0x00). This allows the
ADF7023-J memory to be accessed while the radio is transi-
tioning between states.
Table 27. Summary of SPI Memory Access Commands
SPI Command
SPI_MEM_WR
SPI_MEM_RD
SPI_MEMR_WR
SPI_MEMR_RD
SPI_NOP
MOSI
CS
SPI MEMORY ACCESS COMMAND
Command Value
0x18 (packet RAM),
0x19 (BBRAM),
0x1B (MCR),
0x1E (program RAM)
0x38 (packet RAM),
0x39 (BBRAM),
0x3B (MCR)
0x08 (packet RAM),
0x09 (BBRAM),
0x0B (MCR)
0x28 (packet RAM),
0x29 (BBRAM),
0x2B (MCR)
0xFF
5 BITS
Figure 64. SPI Memory Access Command/Address Format
MEMORY ADDRESS
Description
Write data to BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to
identify memory locations. The most significant three bits of the address are
incorporated into the command (xxxb). This command is followed by the remaining
eight bits of the address.
Read data from BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to
identify memory locations. The most significant three bits of the address are
incorporated into the command (xxxb). This command is followed by the remaining
eight bits of the address, which is subsequently followed by the appropriate number
of SPI_NOP commands.
Write data to BBRAM, MCR, or packet RAM nonsequentially.
Read data from BBRAM, MCR, or packet RAM nonsequentially.
No operation. Use for dummy writes when polling the status word. Also used as
dummy data on the MOSI line when performing a memory read.
BITS[10:0]
MEMORY ADDRESS
Rev. 0 | Page 51 of 100
BITS[7:0]
Block Write
MCR, BBRAM, and packet RAM memory locations can be
written to in block format using the SPI_MEM_WR command.
The SPI_MEM_WR command code is 00011xxxb, where xxxb
represent Bits[10:8] of the first 11-bit address. If more than one
data byte is written, the write address is automatically incremented
for every byte sent until CS is set high, which terminates the
memory access command (see
maximum block write for the MCR, packet RAM, and BBRAM
memories is 256 bytes, 256 bytes, and 64 bytes, respectively.
These maximum block-write lengths should not be exceeded.
Example
Write 0x00 to the ADC_CONFIG_HIGH register
(Address 0x35A).
•
•
•
•
•
Thus, 0x1B, 0x5A, 0x00 is written to the part.
The first five bits of the SPI_MEM_WR command are 00011.
The 11-bit address of ADC_CONFIG_HIGH is
01101011010.
The first byte sent is 00011011 or 0x1B.
The second byte sent is 01011010 or 0x5A.
The third byte sent is 0x00.
DATA BYTE
n × 8 BITS
DATA
Figure 65
for more details). The
ADF7023-J