adf7023-j Analog Devices, Inc., adf7023-j Datasheet - Page 54

• Manufacturer Part Number: adf7023-j
• Description: High Performance, Low Power, Ism Band Fsk/gfsk/msk/gmsk Transceiver Ic
• Manufacturer: Analog Devices, Inc.

ADF7023-J
LOW POWER MODES
The ADF7023-J can be configured to operate in a broad range
of energy sensitive applications where battery lifetime is critical.
This includes support for applications where the ADF7023-J is
required to operate in a fully autonomous mode or applications
where the host processor controls the transceiver during low power
mode operation. These low power modes are implemented using a
hardware wake-up controller (WUC), a firmware timer, and the
smart wake mode functionality of the on-chip communications
processor. The hardware WUC is a low power WUC that comprises
a 16-bit wake-up timer with a programmable prescaler. The
32.768 kHz RCOSC or XOSC provides the clock source for
the timer.
The firmware timer is a software timer residing on the ADF7023-J.
The firmware timer is used to count the number of WUC timeouts
and can be used to count the number of ADF7023-J wake-ups.
Table 28. Settings for Low Power Modes
Low Power
Mode
Deep Sleep
Modes
WUC
WUC
WUC
WUC
WUC
WUC
WUC
Firmware
Timer
Firmware
Timer
Firmware
Timer
SWM
SWM
Memory
Address
0x30D
0x30C
0x30D
0x30D
0x30D
0x30D
0x30E
0x30F
0x101
0x100
0x102,
0x103
0x104,
0x105
0x11A
0x11A
2
1
2
1
1
1
1
1
,
Register Name
WUC_CONFIG_LOW
WUC_CONFIG_HIGH
WUC_CONFIG_LOW
WUC_CONFIG_LOW
WUC_CONFIG_LOW
WUC_CONFIG_LOW
WUC_VALUE_HIGH
WUC_VALUE_LOW
INTERRUPT_MASK_1
INTERRUPT_MASK_0
NUMBER_OF_WAKEUPS_0
NUMBER_OF_WAKEUPS_1
NUMBER_OF_WAKEUPS_IRQ_
THRESHOLD_0
NUMBER_OF_WAKEUPS_IRQ_
THRESHOLD_1
MODE_CONTROL
MODE_CONTROL
Bit
WUC_BBRAM_EN
WUC_PRESCALER[2:0]
WUC_RCOSC_EN
WUC_XOSC32K_EN
WUC_CLKSEL
WUC_ARM
WUC_TIMER_VALUE[15:0]
WUC_TIMEOUT
INTERRUPT_NUM_WAKEUPS
NUMBER_OF_WAKEUPS[15:0]
NUMBER_OF_WAKEUPS_IRQ_
THRESHOLD[15:0]
SWM_EN
SWM_RSSI_QUAL
Rev. 0 | Page 54 of 100
The WUC and the firmware timer, therefore, provide a real-time
clock capability.
Using the low power WUC and the firmware timer, the SWM
firmware allows the ADF7023-J to wake up autonomously from
sleep without intervention from the host processor. During this
wake-up period, the ADF7023-J is controlled by the communi-
cations processor. This functionality allows carrier sense, packet
sniffing, and packet reception while the host processor is in
sleep, thereby dramatically reducing overall system current
consumption. The smart wake mode can then wake the host
processor on an interrupt condition. An overview of the low
power mode configuration is shown in Figure 69, and the
register settings that are used for the various low power modes
are described in Table 28.
Description
0: BBRAM contents are not retained during
PHY_SLEEP.
1: BBRAM contents are retained during
PHY_SLEEP.
Sets the prescaler value of the WUC.
Enables the 32.768 kHz RC OSC.
Enables the 32.768 kHz external OSC.
Sets the WUC clock source.
1: RC OSC selected.
2: XOSC selected.
Enable to ensure that the device wakes
from the PHY_SLEEP state on a WUC
timeout.
The WUC timer value.
WUC Interval(s) = WUC_TIMER_VALUE ×
Enables the interrupt on a WUC timeout.
Enabling this interrupt enables the
firmware timer. Interrupt is set when the
NUMBER_OF WAKEUPS count exceeds the
threshold.
Number of ADF7023-J wake-ups.
Threshold for the number of ADF7023-J
wake-ups. When exceeded, the ADF7023-J
exits low power mode.
Enables smart wake mode.
Enables RSSI prequalification in smart
wake mode.
2
(
WUC_PRESCA
32,768
LER
+
1)