ak4647 AKM Semiconductor, Inc., ak4647 Datasheet - Page 22

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ak4647

Manufacturer Part Number
ak4647
Description
Stereo Codec With Mic/hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ASAHI KASEI
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4647 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (see Table 5).
MS0566-E-00
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
Figure 14. PLL Slave Mode 1 (PLL Reference Clock: LRCK or BICK pin)
AK4647
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
≥ 32fs
1fs
- 22 -
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz,
MCLK
BCLK
LRCK
SDTI
SDTO
DSP or μP
[AK4647]
2006/11

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