ak4626a AKM Semiconductor, Inc., ak4626a Datasheet - Page 29

• Manufacturer Part Number: ak4626a
• Description: High Performance Multi-channel Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0397-E-00
(2) I
AK4626A supports the standard-mode I
I
Figure 17 shows the data transfer sequence at the I
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (Figure 18). The most significant five bits of the slave address are fixed as “00100”. The next
two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The
hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4626A and R/W
bit is “0”, the AK4626A generates the acknowledge and the write operation is executed. If R/W bit is “1”, the
AK4626A generates the not acknowledge since the AK4626A can be only a slave-receiver. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 22).
The second byte consists of the address for control registers of the AK4626A. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The
format is MSB first, 8bits (Figure 20). The AK4626A generates an acknowledge after each byte has been received.
A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on
the SDA line while SCL is HIGH defines a STOP condition (Figure 20).
The AK4626A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4626A generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address
exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and the STOP
condition.
2
2
C-bus system (max:400kHz). The CSN pin should be connected to DVDD at the I
C-bus Control Mode (I2C= “H”)
SDA
D7
0
*
S
T
A
R
T
S
Slave
Address
Figure 17. Data transfer sequence at the I
D6
(Those CAD1/0 should match with CAD1/0 pins)
0
*
Figure 20. Byte structure after the second byte
R/W
A
C
K
Sub
Address(n)
D5
1
*
2
Figure 19. The second byte
C-bus (max:100kHz). Then AK4626A does not support a fast-mode
Figure 18. The first byte
(*: Don’t care)
A
C
K
A4
D4
2
0
C-bus mode. All commands are preceded by a START condition.
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Data(n)
A3
D3
0
A
C
K
Data(n+1)
CAD1
2
A2
D2
C-bus mode
A
C
K
CAD0
A1
D1
2
A
C
K
C-bus mode.
Data(n+x)
R/W
A0
D0
A
C
K
S
T
O
P
P
[AK4626A]
2005/06