ispgal22v10c-7lk Lattice Semiconductor Corp., ispgal22v10c-7lk Datasheet - Page 10

• Manufacturer Part Number: ispgal22v10c-7lk
• Description: In-system Programmable E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

An electronic signature (ES) is provided in every ispGAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when compil-
ing a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically an
ispGAL22V10 and a ispGAL22V10-UES (UES = User Electronic
Signature) or ispGAL22V10-ES. This allows users to maintain
compatibility with existing 22V10 designs, while still having the
option to use the GAL device's extra feature.
The JEDEC map for the ispGAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However, the
ispGAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
A security cell is provided in every ispGAL22V10 device to
prevent unauthorized copying of the array patterns. Once pro-
grammed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-programming
the device, so the original configuration can never be examined
once this cell is programmed. The Electronic Signature is always
available to the user, regardless of the state of this control cell.
ispGAL22V10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with n-
channel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCR induced latching.
The ispGAL22V10 device uses a standard 22V10 JEDEC fusemap
file to describe the device programming information. Any third
party logic compiler can produce the JEDEC file for this device.
The ispGAL22V10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
the power is turned off.
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
In-System Programmability
2
CMOS cells will not lose the pattern even when
10
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the pro-
gramming. The interface signals are Serial Data In (SDI), Serial
Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control.
For details on the operation of the internal state machine and
programming of ispGAL22V10 devices please refer to the ISP
Architecture and Programming section in this Data Book.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The ispGAL22V10 device includes circuitry that allows each
registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing
test vectors perform output register preload automatically.
ispGAL22V10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than
bipolar TTL devices.
All input and I/O pins (except SDI on the ispGAL22V10C) also
have built-in active pull-ups. As a result, floating inputs will float
to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has a
built-in pull-down to keep the device out of the programming state
if the pin is not actively driven. However, Lattice Semiconductor
recommends that all unused inputs and tri-stated I/O pins be
connected to an adjacent active input, Vcc, or ground. Doing so
will tend to improve noise immunity and reduce Icc for the device.
(See equivalent input and I/O schematics on the following page.)
Output Register Preload
Input Buffers
Specifications ispGAL22V10
-20
-40
-60
0
0
1.0
Typical Input Current
Input Voltage (Volts)
2.0
3.0
4.0
5.0