ispgal22v10c-7lk Lattice Semiconductor Corp., ispgal22v10c-7lk Datasheet - Page 9

• Manufacturer Part Number: ispgal22v10c-7lk
• Description: In-system Programmable E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
L O G I C
A R R A Y
LOGIC
ARRAY
t
su +
f
max with No Feedback
t
s u
t
h
300Ω
300Ω
300Ω
R
∞
∞
1
REGISTER
R EG I S T E R
CLK
C L K
390Ω
390Ω
390Ω
390Ω
390Ω
R
3ns 10% – 90%
2
t
GND to 3.0V
See Figure
su+
t
c o
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
9
FROM OUTPUT (O/Q)
UNDER TEST
Specifications ispGAL22V10
*C
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
L
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
LOGIC
ARRAY
R
2
t
cf
+5V
t
pd
REGISTER
CLK
R
1
t
su+
C *
L
t
cf)
TEST POINT