ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 23

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
• Internal Input System Clock (IICLK)
Table F1-2-1 (4) Compliance with Luminance-Color Difference Phase Reversal
The IICLK is IICLK = ICLK in 16-bit 4:2:2 mode whereas in 8-bit 4:2:2 mode and ITU-R BT.656 mode
it is the clock pulse obtained by internally frequency-dividing ICLK to 1/2.
In 8-bit 4:2:2 mode, the position which is two ICLK clocks delayed from the rise of IHS is used for
resetting and IICLK is generated by frequency-dividing ICLK to 1/2.
Normally reset of IICLK presumes the rise position of positive polarity IHS (IHSINV = 0), but by setting
IHES (SUB:41h-bit[5]) and IHSINV, selection of compliance with negative polarity IHS and fall
position is also possible.
In ITU-R BT 656 mode, ICLK is frequency-divided to 1/2 based on SAV.
In 8-bit 4:2:2 mode, if the phase of IHS for luminance and color difference data reverses (number of
ICLKs from IICLK reset to initial color difference data is odd), it is possible to avoid the reversal by
setting ICINV (SUB:41h-bit[4]).
8bit4:2:2 mode
#IICLK
#IICLK
YI[7:0]
Reset
ICLK
IHS
ICINV
IHES
0
1
0
1
0
1
#: Internal signal
Number of ICLKs from IICLK reset to initial color difference data is even.
Number of ICLKs from IICLK reset to initial color difference data is odd.
Figure F1-2-1 (2) IICLK Phase Timing Example
IHSINV
Table F1-2-1 (3) IICLK Reset Position
0
0
1
1
Positive polarity IHS rise (horizontal sync front edge)
Positive polarity IHS fall (horizontal sync rear edge)
Negative polarity IHS fall (horizontal sync front edge)
Negative polarity IHS rise (horizontal sync rear edge)
Usage conditions (8-bit 4:2:2 mode)
Reset position
Crn
Yn
Cbn
PEDL87V2105-02
Yn+1
ML87V2105
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