92hd89d Integrated Device Technology, 92hd89d Datasheet - Page 36

• Manufacturer Part Number: 92hd89d
• Description: Eight Channel Hd Audio Codec Low Power Optimized For Ecr15b And Eup
• Manufacturer: Integrated Device Technology

92HD89D
Eight channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
2.20. HD Audio ECR 15b support
2.21. Digital Core Voltage Regulator
2.19.3. Digital Microphone/GPIO Selection
2.19.4. Vref_Out/GPIO Selection
2.19.5. EAPD/SPDIF_IN/SPDIF_OUT/GPIO0 Selection
2 functions are available on the DMIC_CLK/GPIO3, the DMIC_0/GPIO4, and the DMIC_1/GPIO6
pins. To determine which function is enabled, the order of precedence is followed:
1. If GPIOs are not enabled through the AFG, then at reset, the pins are pulled low by an internal
2. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone
2 functions are available on the VrefOut-A/GPIO1 and VrefOut-E/GPIO2 pins. To determine which
function is enabled, the order of precedence is followed:
1. If GPIO is enabled for that pin, it overrides the VrefOut function for that pin.
2. If the GPIO function is not enabled for that pin, then the VrefOut function is enabled and in its
4 functions are available on the EAPD/SPDIF_IN/SPDIF_OUT1/GPIO0 pin. To determine which
function is enabled, the order of precedence is followed:
1. Default at power-on is EAPD
2. If GPIO is enabled for that pin, it overrides the SPDIF_IN, SPDIF_OUT and EAPD functions for
3. If the GPIO function is not enabled for that pin, then the SPDIF_IN or SPDIF_OUT function may
Although ECR15b is not yet complete (not a DCN), the 92HD89D will implement complete support
for the specification building on the support already present in previous products. ECR 15b features
supported are:
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The digital core operates fat 1.5V. Many systems require that the CODEC use a single 3.3V digital
supply, so an integrated regulator is included on die. The regulator uses pin 9, DVDD, as its voltage
source. The output of the LDO is connected to pin 1 and the digital core. A 10uF capacitor must be
placed on pin 1 for proper load regulation and regulator stability.
pull-down resistor.
path will be mute.
programmed state.
that pin.
be enabled by setting the pin input or output enable to 1, respectively. (Setting input and output
enable to 1 at the same time will only enable SPDIF_IN)
Persistence of many configuration options through bus and function group reset.
The ability to support port presence detect in D3 even when the HD Audio bus is in a low power
state (no clock.)
Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.
Notification if persistent register settings have been unexpectedly reset.
SPDIF active in D3 (required)
The ability to notify the driver that a clock is necessary so entering D3 with the clock stopped is
not permissible.
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92HD89D