92hd89d Integrated Device Technology, 92hd89d Datasheet - Page 64

• Manufacturer Part Number: 92hd89d
• Description: Eight Channel Hd Audio Codec Low Power Optimized For Ecr15b And Eup
• Manufacturer: Integrated Device Technology

92HD89D
Eight channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.
Field Name
Data5
Data4
Data3
Data2
Data1
Data0
Reg
Get
Set
7.4.12. AFG (NID = 01h): GPIOEn
Byte 4 (Bits 31:24)
Bits
5
Data for GPIO5. If this GPIO bit is configured as Sticky (edge-sensitive) imput,
it can be cleared by writing “0”. For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
4
Data for GPIO4. If this GPIO bit is configured as Sticky (edge-sensitive) imput,
it can be cleared by writing “0”. For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
3
Data for GPIO3. If this GPIO bit is configured as Sticky (edge-sensitive) imput,
it can be cleared by writing “0”. For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
2
Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
1
Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
0
Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22.
Byte 3 (Bits 23:16)
R/W
RW
RW
RW
RW
RW
RW
F1600h
Default
0h
0h
0h
0h
0h
0h
64
Byte 2 (Bits 15:8)
Reset
POR-DAFG-ULR
POR-DAFG-ULR
POR-DAFG-ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Byte 1 (Bits 7:0)
716h
V1.0 04/10
92HD89D