htrc110 NXP Semiconductors, htrc110 Datasheet - Page 9

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htrc110

Manufacturer Part Number
htrc110
Description
Hitag Reader Chip
Manufacturer
NXP Semiconductors
Datasheet

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HTRC110 Hitag Reader Chip
Before the system is switched into WRITE_TAG-mode, the demodulator has to be frozen. This is
internally done by clamping the input of the amplifier/filter unit to QGND. Doing so avoids large
transients in the amplifier and the digitizer, which could affect settling times. In addition to the
clamping, there exist other means in the HTRC110, which allow further reduction of the settling
times. All the parts of the circuitry, which are associated with these functions, are controlled by the
FREEZE0, FREEZE1 and THRESET bits, which are located in configuration page 2.
For more details concerning WRITE Timing, Demodulator Setting, Power Up Sequence, etc. please
refer to the HTRC110 application note.
8.6.
The HTRC110 can be switched into idle mode via setting the PD-bit and resetting the PD_MODE-
bit. In this idle mode, only the oscillator and a few other system components are active.
It is also possible to switch the IC completely off. This is achieved by the power-down mode
(PD=1, PD_MODE=1). Within this mode also the clock oscillator is switched off. This reduces the
supply current of the HTRC110 to less than 20µA.
8.7.
The communication between the HTRC110 and the microcontroller is done via a three wire digital
interface. The interface is operated by the following signals:
SCLK
DIN
DOUT
SCLK and DIN are realized as Schmitt-Trigger inputs. DOUT is an open drain output with internal
pullup resistor.
Every communication between HTRC110 and microcontroller begins with an initialization of the
serial interface. The interface initialization condition is a low-to-high transition of the signal DIN
while SCLK is high.
-
or during the communication (after sending the write pulses and before receiving the answer
of the transponder), if the tag is moving.
Idle and Power-down Mode
Serial Interface
Clock
Data Input
Data Output
Figure 4: Serial Signaling
Page 9 of 30
Rev. 3.0
July 2006

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