am79c974 Advanced Micro Devices, am79c974 Datasheet
am79c974
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am79c974 Summary of contents
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... PRELIMINARY Am79C974 TM PCnet -SCSI Combination Ethernet and SCSI Controller for PCI Systems DISTINCTIVE CHARACTERISTICS PCI Features Direct glueless interface to 33 MHz, 32-bit PCI local bus 132 Mbyte/s burst DMA transfer rate Compliant to PCI local bus Specification Revision 2.0 Ethernet Features Supports ISO 8802-3 (IEEE/ANSI 802.3) and ...
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... RISC processor. This results in a smaller die size giving the Am79C974 superior price/performance ver- sus competitive offerings. AMD supports the Am79C974 with a total system solu- tion which includes: A full suite of licensable SCSI drivers and utilities fully tested under the following operating system environments: — ...
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... FIFO & FIFO DMA Control 96 Bytes PCI Data/Address SCSI Control DMA Registers RCV FIFO PCI Host Control and Interface Am79C974 AMD 10Base-T, AUI Ports 802.3 MAC Core FIFO XMT Control FIFO DMA Registers DMA Control 18681A-1 ...
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... AMD Cache SRAM Control Address CPU Data PCnet-SCSI (Am79C974) DRAM Memory Core Logic PCI Bus PC-AT ISA Bus Super I/O IDE/Floppy Ser/Par Am79C974 in a PCI System Am79C974 Video Control PCI to ISA Keyboard Control 18681A-2 ...
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... Am79C974 AMD 1 ...
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... Am79C974 48 ...
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... Am79C974 AMD ...
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... Am79C974 87 ...
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... Figure 25. PCI BIU – DMA Engine – SCSI Block Figure 26. DMA FIFO to SCSI FIFO Interface Figure 27. Am79C974 NAND Tree Test Structure Figure 28. NAND Tree Waveform Figure 29. SCSI Clock Input ...
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... Am79C974 52 ...
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... Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am85C30 Enhanced Serial Communication Controller Bus Mastering Fast SCSI Controller for PCI Systems Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support (IMR+ ) Am79C974 AMD TM TM (ILACC ) TM TM (HIMIB ) 11 ...
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... C/BE2 FRAME 24 IRDY 25 TRDY 26 DEVSEL 27 STOP 28 LOCK 29 VSS 30 PERR 31 SERR 32 VDDB 33 Pin 1 is marked for orientation. RESERVE = Don’t Connect Am79C974 PCnet-SCSI Am79C974 99 XTAL2 98 AVSS2 97 XTAL1 96 AVDD3 95 TXD+ 94 TXP+ 93 TXD- 92 TXP- 91 AVDD4 90 RXD+ 89 RXD- 88 DVSS I/O 87 ...
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... K = Plastic Quad Flat Pack Trimmed and Formed (PQB132) SPEED OPTION Not Applicable Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C974 AMD Valid Combinations 13 ...
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... VDD 92 60 SCSICLK 93 61 VSS 94 BUSY VSS 96 BSY 64 97 ATN 65 98 SCSI^RST 66 99 Am79C974 Pin Name Pin No. Pin Name VSSBS 100 AVSS1 SD0 101 DO– SD1 102 DO+ SD2 103 AVDD1 SD3 104 DI– VSSBS 105 DI+ SD4 106 CI– SD5 ...
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... SD0 102 SD1 84 SD2 109 SD3 79 SD4 88 SD5 113 SD6 114 SD7 111 SDP 110 SEL 112 SERR 24 SLEEP 124 Am79C974 AMD Pin No. Pin Name Pin No. STOP 123 28 TRDY XTAL1 97 117 XTAL2 99 118 TXD– TXD TXP– ...
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... Type Am79C974 Driver # Pins TS3 32 TS3 TS6 1 TS6 OD6 1 TS6 1 TS6 1 TS6 1 TS6 1 TS3 OD6 1 TS6 ...
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... LED Type IOL (mA Am79C974 AMD Driver # Pins OD48 8 OD48 OD48 1 OD48 1 OD48 1 OD48 1 1 OD48 ...
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... CI+/– DI+/– XTAL1 XTAL2 DO+/– RXD+/– TXD+/– TXP+/– EEDI/LINKST EECS EESK/LED1 EEDO/LED3 SD [7:0] SDP PCnet-SCSI MSG (Am79C974) C/D I/O ATN BSY SEL SCSI^RST REQ ACK SCSI CLK RESERVE PWDN BUSY VDD VSS Am79C974 Ethernet SCSI Power Management Signals Test Interface 18248B-4 ...
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... Am79C974’s SCSI controller. The Am79C974 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active REQA from the Am79C974 controller, the controller will actively drive the AD[31:00], C/ BE[3:0], and PAR lines. When RST is active, GNTA is an input for NAND tree testing ...
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... Input/Output, Active Low, Open Drain This signal is asserted for one CLK by the PCnet-SCSI controller when it detects a parity error during any data phase when its AD[31:00] lines are inputs. The PERR pin is only active when PERREN (bit 6) in the PCI com- mand register is set. Am79C974 ...
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... REQA Bus Request Input/Output, Active Low The Am79C974’s SCSI controller asserts REQA pin as a signal that it wishes to become a bus master. Once as- serted, REQA remains active until GNTA has become active. When RST is active, REQA is an input for NAND tree testing ...
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... Microwire EEPROM’s Clock pin con- trolled by either the PCnet-SCSI controller directly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1. The EESK pin is also used during EEPROM Auto-detec- tion to determine whether or not an EEPROM is present Am79C974 ...
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... Operates at pseudo ECL levels. Twisted-Pair Interface RXD 10BASE-T Receive Data Input 10BASE-T port differential receivers. TXD 10BASE-T Transmit Data Output 10BASE-T port differential drivers. TXP 10BASE-T Pre-Distortion Control Output These outputs provide transmit pre-distortion control in conjunction with the 10BASE-T port differential drivers. Am79C974 AMD 23 ...
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... This signal is logically equivalent to the SCSI bus signal BSY duplicated so that external logic can be connected to monitor SCSI bus activity. The results of the NAND tree testing can be observed on the BUSY pin where RST is asserted; otherwise, BUSY will reflect the state of the SCSI Bus Signal line BSY (pin 64). Am79C974 ...
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... V supply. VSS/DVSS Refer to Digital Ground (9 Pins) Ground There are 9 ground pins that are used by the internal digital circuitry. VSSB/VSSBS I/O Buffer Ground (11 Pins) Ground There are 11 ground pins that are used by the PCI bus Input/Output buffer drivers. Am79C974 AMD 25 ...
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... AUI connection. SCSI Interfaces The Am79C974 acts as a bridge between the PCI and SCSI buses. As the maximum data transfer rate on the PCI bus is a very high 132 Mbyte/s compared with the SCSI bus 10 Mbyte/s, buffering is required between the two buses ...
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... CLK. One bus interface unit state machine handles accesses where the Am79C974 controller is the bus slave, and another handles ac- cesses where the Am79C974 controller is the bus mas- ter. All inputs are synchronously sampled. All outputs are synchronously generated on the rising edge of CLK. ...
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... AMD Slave Configuration Write The Slave Configuration Write command is used by the host CPU to write the configuration space in the Am79C974 controller. This allows the host CPU to CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP IDSEL control basic activity of the device, such as enable/dis- able, change I/O location, etc ...
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... Slave I/O Read The Slave I/O Read command is used by the host CPU to read the Am79C974’s CSRs, BCRs and EEPROM lo- cations and SCSI and CCB registers single cycle, non-burst 8-bit,16-bit or 32-bit transfer which is initiated by the host CPU. The typical number of wait states added to a slave I/O read access on the part of the Am79C974 controller clock cycles ...
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... initiated by the host CPU. The typical number of wait states added to a slave I/O write access on the part of the Am79C974 controller clock cycles. The Am79C974 controller will not produce Slave I/O write commands while being a bus master. ...
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... REQ signal and ownership is granted by the arbiter through the GNT signal. Figure 5 shows the Am79C974 controller bus acquisi- tion. GNT is asserted at clock 3. The Am79C974 control- ler starts driving AD[31:00] and C/BE[3:0] prior to clock 4. FRAME is asserted at clock 5 indicating a valid ad- dress and command on AD[31:00] and C/BE[3:0] ...
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... AMD Bus Master DMA Transfers There are four primary types of DMA transfers. The Am79C974 controller uses non-burst as well as burst cycles for read and write access to the main memory. Basic Non-Burst Read Cycles All Am79C974 controller non-burst read accesses are of the PCI command type Memory Read (type 6). Note that ...
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... Figure 7 shows two non-burst read access within one ar- bitration cycle. The Am79C974 controller will drop FRAME between two consecutive non-burst read cy- cles. The Am79C974 controller will re-request the bus right again preempted before starting the second CLK FRAME AD C/BE PAR ...
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... All Am79C974 controller non-burst write accesses are of the PCI command type Memory Write (type 7). Figure 8 shows two non-burst write access within one arbitration cycle. The Am79C974 controller will drop FRAME between two consecutive non-burst write cy- cles. The Am79C974 controller will re-request the bus CLK ...
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... All Am79C974 controller burst read transfers are of the PCI command type Memory Read Line (type14). AD[1:0] will both be ZERO during the address phase in- dicating a linear burst order. All four byte enable signals will be ZERO during the data phase as the Am79C974 controller always reads a full 32-bit word when in burst CLK 1 ...
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... AMD Basic Burst Write Cycles All Am79C974 controller burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be ZERO during the address phase indicating a lin- ear burst order. All four byte enable signals will be ZERO during the data phase as the Am79C974 controller al- ways writes a full 32-bit word when in burst mode ...
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... FRAME and IRDY are both deasserted, indicating an IDLE cycle. Target Initiated Termination When the Am79C974 controller is a bus master, the cy- cles it produces on the PCI bus may be terminated by the target in one of three different ways: Disconnect with data transfer, disconnect without data transfer, and tar- get abort ...
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... cycle later with the deassertion of IRDY. It finally re- leases the bus on clock 6. The Am79C974 controller will re-request the bus after 2 clock cycles to retry the last transfer. The starting address of the new transfer will be the same address as of the last untransferred data. ...
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... Since data integrity is not guaranteed, the Am79C974 controller cannot recover from a target abort event. For Ethernet, the Am79C974 controller will reset all CSR and BCR locations to their H_RESET values. Any on- going network activity will be stopped immediately. The PCI configuration registers will not be cleared ...
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... AMD Master Initiated Termination There are three scenarios besides normal completion of a transaction where the Am79C974 controller will termi- nate the cycles it produces on the PCI bus. These are Preemption with and without FRAME assertion and Master Abort. Preemption When FRAME is Deasserted ...
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... Preemption When FRAME is Asserted The central arbiter can take GNT to the Am79C974 con- troller away if the current bus operation takes too long. This may happen, for example, when the Am79C974 controller tries to fill the whole Ethernet transmit FIFO and the target inserts extra wait states for every data phase ...
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... The Am79C974 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C974 controller. For the Ethernet, the Am79C974 controller will reset all CSR and BCR locations to their H_RESET values. Any on-going network activity will be stopped immediately ...
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... This means that the software must clear the descriptor own bits and reset its descrip- tor ring pointers before the restart of the Am79C974 controller. The reload of descriptor base addresses is performed in the LANCE only after initialization re- ...
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... base address of both the transmit and receive descriptor rings into CSRs for use by the Am79C974 controller dur- ing subsequent operations. As the final step in the self-initialization process, the base address of each ring is loaded into each of the cur- ...
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... Rcv Buffer Buffer Buffers DESCRIPTOR RINGS Xmt Descriptor RX DESCRIPTOR RINGS Ring 1st desc. start TMD0 TMD1 TMD2 TMD3 Data Xmt Buffer Buffer Buffers 1 Am79C974 AMD • • • 2nd desc. start RMD0 Data Data Buffer • • ...
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... TDTE at the next expiration of the poll time count. If the OWN bit of the TDTE is set, but Start of Frame (STP) bit is not set, the Am79C974 controller will imme- diately request the bus in order to reset the OWN bit of this descriptor. (This condition would normally be found following a LCOL or RETRY error that occurred in the middle of a transmit frame chain of buffers ...
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... Am79C974 controller will immediately access the next descriptor and find the condition OWN=1 and STP=0 as described earlier. As described for that case, the Am79C974 controller will reset the own bit for this de- scriptor and continue in like manner until a descriptor with OWN=0 (no more transmit frames in the ring) or OWN=1 and STP=1 (the first buffer of a new frame) is reached ...
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... AMD Receive Descriptor Table Entry (RDTE) If the Am79C974 controller does not own both the cur- rent and the next Receive Descriptor Table Entry then the Am79C974 controller will continue to poll according to the polling sequence described above. If the receive descriptor ring length is 1, then there is no next descrip- tor to be polled ...
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... SFD) have been received, the MAC engine will automatically delete the frame from the Receive FIFO, without host intervention. The Am79C974 controller has the ability to accept runt pack- ets for diagnostics purposes and proprietary networks ...
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... Am79C974 controller will begin timing the second part deferral (InterFrame Spacing Part 2 – IFS2) of 3.6 s. Once IFS1 has completed, and IFS2 has commenced, the Am79C974 controller will not defer to a receive frame if a transmit frame is pending. This means that the Am79C974 controller will not attempt to receive the re- ceive frame, since it will start to transmit, and generate a collision at 9 ...
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... IPG counter will be reset by a worst case IPG shrinkage/fragment sce- nario and the Am79C974 controller will defer its trans- mission. In addition, the Am79C974 controller will not restart the “blinding” period if carrier is detected within the 4.0 s – ...
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... V input (VDD/2) < 0 2.5 V input (VDD/2) the basic timing reference for the MENDEC portion of the Am79C974 controller. The crystal is divided by two, to create the internal transmit clock reference. Both clocks are fed into the MENDECs Manchester Encoder to generate the transitions in the encoded data stream. ...
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... Receiver Path The principal functions of the Receiver are to signal the Am79C974 controller that there is information on the re- ceive pair, and separate the incoming Manchester en- coded data stream into clock and NRZ data. The Receiver section (see Receiver Block Diagram) consists of two parallel paths ...
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... AMD the controller portion of the Am79C974 controller sees the first ISRDCLK transition. This also strobes in the in- coming fifth bit to the MENDEC as Manchester “1”. IRXDAT may make a transition after the ISRDCLK rising edge in bit cell 5, but its state is still undefined. The Manchester “ ...
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... The AUI is the PLS (Physical Layer Signaling) to PMA (Physical Medium Attachment) interface which effec- tively connects the DTE to a MAU. The differential inter- face provided by the Am79C974 controller is fully compliant to Section 7 of ISO 8802-3 (ANSI/IEEE 802.3). After the Am79C974 controller initiates a transmission it will expect to see data “ ...
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... RCV signal going active. If T-MAU is selected using the PORTSEL bits in CSR15, then when moving from AUI to T-MAU selection the T-MAU will be forced into the LINK Fail state. In the Link Fail state, XMT, RCV and COL are inactive. Am79C974 ...
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... Note that the recommended resistor values and filter and transformer modules are the same as those used by the IMR (Am79C980) and the IMR+ (Am79C981). Filter & Transformer Module 61.9 1.21 K 422 XMT 61.9 Filter 422 RCV Filter 100 Am79C974 AMD RJ45 Connector 1:1 TD TD- 1:1 RD RD- 18681A-25 57 ...
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... The PCI interface section is not effected by SLEEP. In particular, access to the PCI configuration space re- mains possible. None of the configuration registers will be reset by SLEEP. All I/O accesses to the Am79C974’s Ethernet controller will result in a PCI target abort response. The first power saving mode is called coma mode. In coma mode, the Am79C974 controller has no means to use the network to automatically wake itself up ...
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... E.G. a read of the Sub-Class register can be performed by reading from offset 08h with only BE2 being active. I/O Resources The Am79C974 controller uses two separate blocks of I/O space, one for the SCSI controller and one for the Ethernet controller. This section discusses the I/O ad dress block used by the Ethernet controller ...
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... WIO mode and immediately thereafter, to enter DWIO mode. Word accesses to non word address boundaries are not allowed while in WIO mode. (A write access may cause unexpected reprogramming of the Ethernet controller control registers. A read access will yield undefined values.) Am79C974 Register APROM APROM APROM APROM APROM ...
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... EEPROM contents that was obtained during the automatic EEPROM read operation that follows the H_RESET operation. Am79C974’s Ethernet Controller I/O Base Address The Ethernet PCI Configuration Space Base Address register defines what I/O base address the Ethernet controller uses. This register is typically programmed by the PCI configuration utility after system power-up ...
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... RDP = Register Data Port. The RDP is used with the RAP to gain access to any of the Am79C974 controller CSR locations. Access to any of the CSR locations of the Am79C974 controller is performed through the Am79C974 control- lers Register Data Port (RDP). In order to access a par- ticular CSR location, the Register Address Port (RAP) should first be written with the appropriate CSR ad- dress ...
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... RST pin (H_RESET). A RST pin assertion will cause the REQ signal to deassert within six clock cycles following the assertion. In the RST pin case, the Am79C974 con- troller will not wait for the assertion of the GNT signal be- fore deasserting the REQ signal. ...
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... Slave Access to I/O Resources The Am79C974 device is always a 32-bit peripheral on the system bus. However, the width of individual soft- ware resources on board the Am79C974 controller may be either 16-bits or 32-bits. The Am79C974 controller I/O resource widths are determined by the setting of the ...
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... Table 4 describes all possible bus slave accesses that may be directed toward the Am79C974 controller. (i.e., the Am79C974 controller is the target device during the transfer.) The first column indicates the type of slave ac- cess. RD stands for READ, WR for a WRITE operation. ...
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... EEPROM will be pre- served at system power-down.) When the PREAD bit of BCR19 is set, it will cause the Am79C974 controller to terminate further accesses to internal I/O resources with the PCI retry cycle. Accesses to the PCI configuration space is still possible ...
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... APROM offsets within the Am79C974 I/O resources map. Startup code in the sys- tem BIOS can perform the PCI configuration accesses, the IESRWE bit write, and the APROM writes. Direct Access to the Microwire Interface The user may directly access the Microwire port through the EEPROM register, BCR19 ...
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... The value of this byte should be such that the total checksum for the entire 36 bytes of EEPROM data equals the value FFh. The checksum ad- just byte is needed by the Am79C974 controller in order to verify that the EEPROM contents have not been corrupted. Am79C974 ...
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... Once the last data byte of the frame has completed, prior to appending the FCS, the Am79C974 controller will check to ensure that 544 bits have been transmitted. If not, pad bytes are added to extend the frame size to this value, and the FCS is then added ...
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... If 16 total attempts (initial attempt plus 15 retries) fail, the Am79C974 controller sets the RTRY bit in the current transmit TDTE in host memory (TMD2), gives ...
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... All receive frames can be accepted by setting the PROM bit in CSR15. When PROM is set, the Am79C974 con- troller will attempt to receive all messages, subject to minimum frame enforcement. Promiscuous mode over rides the effect of the Disable Receive Broadcast bit on receiving broadcast frames ...
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... Normal events which may occur and which are handled autonomously by the Am79C974 controller are basically collisions within the slot time and automatic runt packet rejection. The Am79C974 controller will ensure that col- lisions which occur within 512 bit times from the start of reception (excluding preamble) will be automatically de- leted from the receive FIFO with no host intervention ...
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... Ex- ternal loopback tests will transmit frames onto the network if the AUI port is selected, and the Am79C974 controller will receive network traffic while configured for external loopback when the AUI port is selected. Runt Packet Accept is automatically enabled when any loop- back mode is invoked ...
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... RESET operation: H_RESET H_RESET= HARDWARE_RESET is a Am79C974 RE- SET operation that has been created by the proper as- sertion of the RST PIN of the Am79C974 device. When the minimum pulse width timing as specified in the RST pin description has been satisfied, then an internal RE- Default SET operation will be performed ...
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... In a normal operation, both sets of registers must be pro- grammed with the specifics of the transfer, such as start- ing address, transfer count, etc. (For more information, refer to Technical Manual PID #18738A). SCSI Specific DMA Engine The SCSI Specific DMA Engine in the Am79C974 pro- 32 Data PCI Bus ...
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... Funneling Logic Figure 26 shows the internal DMA logic interface with the SCSI block. The DMA FIFO interfaces to the Funnel Am79C974 ...
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... Starting Transfer Count (bits 31:0 used) Starting Physical Address Working Byte Counter (bits 31:0 used) Working Address Counter (bits 31:8 reserved, bits 7:0 used) Status Register Starting Memory Descriptor List (MDL) Address Working MDL Counter Am79C974 AMD 16-Byte SCSI FIFO 18681A-30 Type R/W R/W R ...
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... ABORT 1 1 START DMA Scatter-Gather Mechanism The Am79C974 controller contains a scatter-gather translation mechanism which facilitates faster data transfers. This feature uses a Memory Descriptor List which is stored in system memory. Use of the Memory Descriptor List allows a single SCSI transfer to be read from (or written to) non-contiguous physical memory lo- cations ...
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... Starting Offset WAC register (bits 11:0) has rolled over to ‘00h’, the WAC now points to the beginning of the Page Frame Address #2 as shown below. The WMAC is then incremented to point to the next entry in the MDL Am79C974 AMD MDL 12 0 Ignored Ignored Ignored Ignored ...
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... DMA Command Register ((B)+40h) must be set to enable this interrupt) An interrupt from the SCSI block will automatically set bit 4 (SCSIINT) in the DMA Status register (Address (B)+54h). The SCSI block will generate an interrupt un- der the following conditions: SCSI Reset occurred Am79C974 4K Page #n Data 18681A/1-34 ...
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... REQ/ACK Control Parity Reset Levels SCSI Block ID The Am79C974 contains a SCSI Block ID code which is stored in the MSB of the Current Transfer Count Regis- ter. The code reflects the chip’s revision level and family code. This 8-bit code may be read when the following conditions are true ...
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... AMD When this feature is enabled, the Am79C974 will check parity on all data received from the SCSI bus. Any de- tected error will be flagged by setting bit 5 in the SCSI Status Register, and ATN will be asserted on the SCSI bus. However, no interrupt will be generated. When this feature is disabled (bit 4 set to ‘0’), no parity check is done on incoming bytes ...
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... Note: Command stacking should only be used during SCSI Data In or Data Out transfers. Invalid Commands When an illegal command is written to the Am79C974, the Invalid Command Bit (Bit 6, Register (B)+14h) will be Code set to ‘1’, and an interrupt will be generated to the host. ...
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... When the Target asserts REQ, a Service Request interrupt is generated. In the Message In phase when the device receives the last byte. The Am79C974 keeps the ACK sig- nal asserted and generates a Successful Opera- tion interrupt. During Synchronous Data transfers the Target may send up to the maximum synchronous offset number of REQ pulses to the Initiator ...
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... SCSI bus. Although an actual DMA request is not made, DMA interface must be enabled when pad bytes are transmit- ted since the Am79C974 uses the Current Transfer Count Register to terminate transmission. This command terminates under the same conditions as ...
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... Selection or Reselection. Upon disconnecting from the bus the Selection/ Reselection circuit is automatically disabled by the de- vice. This circuit must be enabled for the Am79C974 to respond to subsequent reselection attempts and the En- able Selection/Reselection Command is issued to do that. This command is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus ...
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... The SCSI Bus activity is reflected by the BUSY output line. This signal, when active, indicates that the SCSI Bus is in use, therefore the Am79C974 should not be powered down. This signal is the logical equivalent to the SCSI bus signal BSY, however not physically connected to the BSY signal on the bus ...
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... AMD NAND Tree Testing The Am79C974 controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus signals (see Figure 27 and Table 8 RST (pin 120) INTA (pin 117) INTB ...
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... IRDY 30 25 TRDY 31 26 DEVSEL 32 27 STOP 33 28 LOCK 34 29 PERR 35 31 SERR PAR 38 35 C/BE1 Am79C974 AMD NAND Tree Input # Pin # Name 39 36 AD15 40 38 AD14 41 39 AD13 42 40 AD12 43 41 AD11 44 42 AD10 45 44 AD9 46 45 ...
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... When testing is complete, deassert RST to exit this test mode. Note that some of the pins connected to the NAND tree are outputs in normal mode of operation. They must not be driven from an external source until the PCnet-SCSI controller is configured for NAND tree testing. 0000FFFF 3 7 Figure 28. NAND Tree Waveform Am79C974 1 18681A-36 ...
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... IOL3 = 12 mA (Note 1) IOH = –2 mA (Note 5) VIN = 0 VIN = VDD, VDDB VOUT = 0.4 V VOUT = VDD, VDDB VIN = External Clock VIN = External Clock VIN = External Clock VIN = VSS VIN = External Clock VIN = VDD Am79C974 AMD . . . . . . . . . . . . . . . . . + VIN AVDD + 0.5 V, VIN VDD + 0.5 V, VIN VDDB + 0.5 V VIN VDDBS + 0 ...
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... MHz Sinusoid, 5 MHz f 10 MHz Sinusoid, 5 MHz f 10 MHz Sinusoid, 5 MHz f 10 MHz LRT = LOW LRT = LOW LRT = LOW LRT = LOW (Note 4) VSS = 0 V VDD = 5 V (Note 4) Am79C974 Min Max Unit –500 +500 A –500 +500 A 630 1200 mV – – ...
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... Test Conditions 4.75 V < VDD < 5.25 V IOH = –2 mA (Note 5) IOL = 48 mA 0.0 V < VIN < 2.7 V 2.7 V < VIN < VDD 0.4 V < VOUT < VDD XTAL1 = 20 MHz, CLK = 33 MHz SLEEP Active Awake Bit Set Active Am79C974 AMD Min Max Unit 2.0 VDD + V 0.5 VSS – 0 ...
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... All PCI Inputs except IDSEL IDSEL VIN = 0 V All SCSI, Ethernet, VI PCI Output and I/O Pins, BUSY CLK (PCI) VIN = 0 V SCSI CLK Pin-to-Pin Human Body Model: 100 pF at 1.5 K All I/O VLU 10 V Am79C974 Min Max Unit –100 +100 mA ...
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... EEPROM timing requirements Test Conditions @ 1 2 0.8 V over 2 V p-p over 2 V p-p (See note below) (See note below) (See note below) (See note below) (See note below) Am79C974 AMD Min Max Unit 0 33 MHz ...
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... Note: Not tested; parameter guaranteed by characterization Test Conditions (10% to 90%) (90% to 10%) (tTM = | tTR – tTF|) (See note below) (See note below) VIN > VTHS (min) VIN > VTHS (min) Am79C974 Min Max Unit 250 350 ns 5 ...
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... CI carrier sense off Test Conditions |VIN| > |VASQ| (Note 1) |VIN| > |VASQ| (Note 2) |VIN| > |VASQ| (Note 3) |VIN| > |VASQ| (Note 4) VIN = External Clock VIN = External Clock VIN = External Clock VIN = External Clock VIN = External Clock Am79C974 AMD Min Max Unit 2.5 5.0 ns 2.5 5.0 ns 1.0 ...
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... Test Conditions Clock Frequency) over 2 V p-p over 2 V p-p * These parameters are not 100% tested, but are evalu- ated at initial characterization and at any time the design is modified where these parameters may be affected. Am79C974 Min Max Unit 14.58 0.65 tCP ns 40 100 ns 54 ...
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... ACK Delay to ACK Delay to ACK Delay to ACK Delay Set Up Time to Data Hold Time to Data Hold Time to Data Hold Time to Data Hold Time SCSI Termination SCSI Termination SCSI Termination SCSI Termination Am79C974 AMD Min Max 55* 90* 90* 100* 25* ...
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... May Change from Don’t Care, Any Change Permitted Does Not Apply Normal and Three-State Outputs Am79C974 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “ ...
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... 52.3 Test Point 154 100 18681A-38 AUI DO Switching Test Circuit DV DD 294 Test Point 294 100 18681A-39 TXD Switching Test Circuit DV DD 715 Test Point 715 100 18681A-40 TXP Outputs Test Circuit Am79C974 AMD 101 ...
Page 102
... PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, IDSEL GNT 102 HIGH 2.4V 2 LOW 1.5 V 0 RISE t FALL t CYC CLK Waveform SU(GNT) Input Setup and Hold Timing Am79C974 2.0 V 1.5 V 0.8 V 18681A- H(GNT) 18681A-42 ...
Page 103
... TRDY, STOP, LOCK, DEVSEL VAL MIN Valid n t VAL(REQ) MIN Valid n Output Valid Delay Timing Valid n t OFF Valid n Output Tri-State Delay Timing Am79C974 AMD Tx MAX Valid n+1 MAX Valid n+1 18681A-43 Tx 18681A-44 103 ...
Page 104
... TXP– t XMTON XMT (Note 1) Note: 1. Internal signal and is shown for clarification only. t PWPLP TXD+ TXP+ TXD– TXP– t PWLP 104 Transmit Timing t PERLP Idle Link Test Pulse Am79C974 t TETD t XMTOFF 18681A-45 18681A-46 ...
Page 105
... SWITCHING WAVEFORMS 10BASE-T Interface RXD RXD Receive Thresholds (LRT=0) Receive Thresholds (LRT=1) Am79C974 AMD V TSQ+ V THS+ V THS– V TSQ– tmau_RCV_LRT_HI 18681A-47 V LTSQ+ V LTHS+ V LTHS– V LTSQ– tmau_RCV_LRT_HI 18681A-48 105 ...
Page 106
... Internal signal and is shown for clarification only. Transmit Timing – End of Frame (Last Bit = 0) 106 DOTR 1 Transmit Timing – Start of Frame Bit (n–1) Bit (n) Am79C974 t X1H t X1L t t X1F X1R DOTF 18681A-49 t DOETD Typical > ...
Page 107
... Note: 1. Internal signal and is shown for clarification only. Transmit Timing – End of Frame (Last Bit = 1) DI+/– V ASQ t PWKDI t PWODI Bit (n–1) Bit (n) Receive Timing Am79C974 AMD t DOETD Typical > 250 ns 18681A-51 t PWKDI 18681A-52 107 ...
Page 108
... AMD AC SWITCHING WAVEFORMS Attachment Unit Interface CI+/– V ASQ t PWOCI DO+/– 108 PWKCI Collision Timing t DOETD 40 mV 100 mV max. 80 Bit Times Port DO ETD Waveform Am79C974 t PWKCI 18681A- 18681A-54 ...
Page 109
... Figure 30. Asynchronous Initiator Transmit All Inputs True Data Outputs SD [7:0], SDP Hi-Z Outputs SD [7:0], SDP All Open Drain Outputs Figure 29. Clock Input Am79C974 AMD 3.0 V 1.5 V 0.0 V VOH 2.0 V VOL VOH – 0.3 V 2.0 V VOL + 0.3 V 2.0 V 0.8 V VOL 18681A-55 6 18681A-56 ...
Page 110
... AMD AC SWITCHING TEST WAVEFORMS SCSI Interface SD [7:0] SDP ACK REQ SD [7:0] SDP REQ ACK SD [7:0] SDP REQ ACK 110 Figure 31. Asynchronous Initiator Receive Figure 32. Synchronous Initiator Transmit Figure 33. Synchronous Initiator Receive Am79C974 11 12 18681A-58 17 18681A-59 20 18681A-60 ...
Page 111
... Product names used in this publication are for identification purposes only and may be trademarks of their respective companies 1.097 1.103 1.075 1.085 Pin 1 ID Top View 0.025 Basic 0.80 REF Side View Am79C974 AMD Pin 33 0.947 0.953 1.075 1.085 1.097 1.103 Pin 2 Pin 132 0.130 ...
Page 112
... Am79C974 Default Value 1022h 2000h 0uuu uu00 00h 00h 00h 02h 00h 00h uuuu uuuu uu 02h Default Value 1022h 2020h 0080h uuuu 00h 00h 00h 01h 00h 00h ...
Page 113
... PADR2: Physical Address Register — PADR[47:32] MODE: Mode Register IADR[15:0]: Alias of CSR1 IADR[31:16]: Alias of CSR2 CRBAL: Current RCV Buffer Address Lower CRBAU: Current RCV Buffer Address Upper CXBAL: Current XMT Buffer Address Lower CXBAU: Current XMT Buffer Address Upper Am79C974 Comments AMD Use ...
Page 114
... Reserved Reserved Reserved SWS: Software Style IR: IR Register PXDAL: Previous XMT Descriptor Address Lower PXDAU: Previous XMT Descriptor Address Upper PXBC: Previous XMT Byte Count PXST: Previous XMT Status NXBA: Next XMT Buffer Address Lower Am79C974 Comments Use ...
Page 115
... Chip ID Register Upper RAEO Register Reserved RCON: Ring Length Conversion Reserved XMTTDR: Transmit Time Domain Reflectometry Count Reserved Reserved Reserved Reserved Reserved MERRTO: Bus Time-Out Reserved Reserved Reserved Reserved Reserved Reserved Reserved Am79C974 Comments AMD Use ...
Page 116
... Reserved Miscellaneous Configuration Reserved Link Status (Default) Receive Status (Default) Reserved Transmit Status (Default) Reserved Reserved Reserved Burst Size and Bus Control EEPROM Control and Status Software Style Reserved Am79C974 Comments Programmability User EEPROM No No Yes No Yes Yes Yes Yes No Yes ...
Page 117
... Start Current Transfer Count Register High Reserved Register Description Command Starting Transfer Count Starting Physical Address Working Byte Counter Working Address Counter Status Register Starting Memory Descriptor List (MDL) Address Working MDL Counter Am79C974 AMD Type Read Write Read Write Read/Write Read/Write Read Write ...
Page 118
... Transmit and receive filters, transformers and common mode chokes. 16-pin 0.3” DIL Transmit and receive filters and transformers. 8-pin 0.3” DIL Transmit and receive common mode chokes. 16-pin 0.3” DIL Transmit and receive filters and transformers, transmit common mode choke. Am79C974 Description ...
Page 119
... Package A553-0506-AB 16-Pin 0.3” DIL TD01-0756K 16-Pin 0.3” DIL TG01-0756W 16-Pin 0.3” SMD EP9531-4 16-Pin 0.3” DIL PE64106 16-Pin 0.3” DIL TLA 100-3E 16-Pin 0.3” DIL LT6031 16-Pin 0.3” DIL Am79C974 AMD Description 100 119 ...
Page 120
... VCO, AMD strongly recommends that the low-pass filter shown below be implemented on these pins. Tests using this filter have shown significantly increased noise immunity and reduced Bit Error Rate (BER) statistics in designs using the PCnet-SCSI controller. 18681A-61 Am79C974 (Pin 96) DD3 (Pin 108) DD2 6.8 F ...
Page 121
... (Pin 103) and AV DD1 These pins provide power for the AUI and twisted-pair receive circuitry. No specific decoupling has been nec- essary on these pins. Am79C974 AMD (Pin 91) DD4 121 ...
Page 122
APPENDIX D Alternative Method for Initialization of Ethernet Controller The Ethernet portion of the PCnet-SCSI controller may be initialized by performing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead ...
Page 123
... SCSI connectors (either one or two depending internal/external support MHz crystal oscillator and regulated terminators (on-board) which can (3.937 in) away from the Am79C974. There are many ways to route SCSI bus traces on a host adapter board or motherboard. Ideally, traces from the ...
Page 124
... Layout #1 This approach avoids the cost of placing an external connector on the motherboard. In this configuration, the Am79C974 is always at one end of the SCSI bus, there- fore, the regulated terminators remain active. This elimi- nates the problem of switching the regulated terminators on or off to accommodate peripheral con- figurations ...
Page 125
... This approach requires the fol- lowing and is illustrated in Figure E-4: An external connector mounted on the mothe- rboard with routings that connect to the Am79C974. The Am79C974 must be as close as possible to this external connector since this part of the SCSI Internal SCSI bus cable Keyboard ...
Page 126
... Connector Termination Figure E-4. Motherboard Layout — Approach #2 Motherboard designs which place an internal and exter- nal connector on either side of the Am79C974 are dis- couraged since: Two SCSI connectors are required on the mothe- rboard—one more than what the other two ap- proaches call for. ...
Page 127
... Decoupling Methods As stated in Appendix C, decoupling capacitors should be used across the VDD and VSS pins on the motherboard There are pairs of VDD and VSS pins on the Am79C974 that should each have their own decoupling capacitor. The following decoupling method should be used for the ...
Page 128
...
Page 129
... This impedance is typically 84 +/– 12 vary greatly with PC board characteristics and cabling. R3-20 are 110 1% 2. Ceramic 150 f Alum µf Tant Figure E-6. Regulated Termination Am79C974 AMD , but can TERMPWR R3-11 DB (0-7,P) R12 ATN R13 BSY R14 ACK R15 RST R16 MSG ...
Page 130
... Scheme #3 In this case, both internal and external SCSI peripherals are used. The regulated terminators should be deacti- vated (since the Am79C974 will sit in the middle of the SCSI bus). This may be accomplished through hard- ware or software. The hardware approach involves de- veloping a mechanism to detect peripherals connected to the SCSI bus ...
Page 131
... INTx (Pins 117 and 118) The Am79C970 and Am53C974 devices have only one interrupt output, which is connected to pin 117. The Am79C974, on the other hand, has two interrupt out- INTA, which is used for SCSI interrupts, is puts: bonded to the die inside the device package. These pins can be driven by any signal without affecting the opera- tion of the device ...
Page 132
... The Am53C974 uses pins 127 and 124 (REQ and GNT) for bus master arbitration, while the Am79C790 uses pins 126 and 123. The Am79C974 uses pins 127 and 124 (REQA and GNTA) for bus arbitration from the SCSI controller, and it uses pins 126 and 123 (REQB and GNTB) for arbitration for the Ethernet controller ...
Page 133
... ADy IRQ1 IRQ2 . MUX . . IRQ15 MUX Control Figure F-1. PCI Family Connections XTAL2 97 XTAL1/SCSICLK2 60 SCSICLK1 127 REQA 124 GNTA 126 REQB 123 GNTB 9 IDSELA 10 IDSELB 117 INTA 118 INTB Am79C974 AMD Am79C970, Am53C974, or Am79C974 18681A-69 133 ...
Page 134
... AMD, the AMD logo, and Am386 are registered trademarks of Advanced Micro Devices, Inc. GLITCH EATER, PCnet HIMIB, MACE, ILACC, IMR+, and Am486 are trademarks of Advanced Micro Devices, Inc. SCSI Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 134 Am79C974 ...
Page 135
... AMENDMENT Am79C974 TM PCnet -SCSI Combination Ethernet and SCSI Controller for PCI Systems This amendment corrects a few minor inaccuracies and adds or clarifies a few sections. Minor corrections should be made on the existing data sheets. However, for ease of use, pages with more than a word or two of corrections are printed with this amendment ...
Page 136
... PIN DESCRIPTION, GNTA Add after the second paragraph: The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active REQA from the Am79C974 controller, the Am79C794 will actively drive the AD[31:00], C/BE[3:0], and PAR lines. Page 20 Note that INTA and INTB are both open drain pins ...
Page 137
... Change SPRINTEN to LAPPEN in lines 12 and 13. Page 54 Line 17, change 100% to 10%. Page 59 Line 12 should read, “When the Am79C974 controller samples its IDSELA or IDSELB input ...” (The original ommitted “IDSELA”). Page 62 Column 2, line 30, change “lower two bytes” to “upper two bytes”. ...
Page 138
... Figure E-5 Decoupling Capacitor Placement Change the names of the following power pins: — Change from VDD3B to VDDB. — Change from VSS3B to VSSB. — Change from VDDB to VDDBS. — Change from VSSB to VSSBS Am79C974 ...
Page 139
... C/BE2 FRAME 24 IRDY 25 TRDY 26 DEVSEL 27 STOP 28 LOCK 29 VSS 30 PERR 31 SERR 32 VDDB 33 Pin 1 is marked for orientation. RESERVE = Don’t Connect Am79C974 PCnet-SCSI Am79C974 AMD 99 XTAL2 98 AVSS2 97 XTAL1 96 AVDD3 95 TXD+ 94 TXP+ 93 TXD- 92 TXP- 91 AVDD4 90 RXD+ 89 RXD- 88 DVSS I/O 87 ...
Page 140
... VDD 92 60 SCSICLK 93 61 VSS 94 BUSY VSS 96 BSY 64 97 ATN 65 98 SCSI^RST 66 99 Am79C974 Pin Name Pin No. Pin Name VSSBS 100 AVSS1 SD0 101 DO– SD1 102 DO+ SD2 103 AVDD1 SD3 104 DI– VSSBS 105 DI+ SD4 106 CI– SD5 ...
Page 141
... SD0 102 SD1 84 SD2 109 SD3 79 SD4 88 SD5 113 SD6 114 SD7 111 SDP 110 SEL 112 SERR 24 SLEEP 124 Am79C974 AMD Pin No. Pin Name Pin No. STOP 123 28 TRDY XTAL1 97 117 XTAL2 99 118 TXD– TXD TXP– ...
Page 142
... LED Type IOL (mA Am79C974 Driver # Pins OD48 8 OD48 OD48 1 OD48 1 OD48 1 OD48 1 1 OD48 ...
Page 143
... Input, Active Low This signal indicates that the access to the bus has been granted to the Am79C974’s SCSI controller. The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active REQA from the Am79C974 controller, the Am79C974 will actively drive the AD[31:00], C/BE[3:0], and PAR lines ...
Page 144
... AMD Bus Master DMA Transfers There are four primary types of DMA transfers. The Am79C974 controller uses non-burst as well as burst cycles for read and write access to the main memory. Basic Non-Burst Read Cycles All Am79C974 controller non-burst read accesses are of the PCI command type Memory Read (type 6). Note that ...
Page 145
... Since data integrity is not guaranteed, the Am79C974 controller cannot recover from a target abort event. For Ethernet, the Am79C974 controller will reset all CSR and BCR locations to their H_RESET values. Any on-going network activity will be stopped immediately. The PCI configuration registers will not be cleared. For ...
Page 146
... The Am79C974 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C974 controller. For the Ethernet, the Am79C974 controller will reset all CSR and BCR locations to their H_RESET values. Any on-going network activity will be stopped immediately ...
Page 147
... SCSI peripheral does not get lost in the DMA FIFO when a Target Disconnect occurs. However, it does not complete the original transfer. The software must now read the SCSI Current Transfer Count register (CTCREG) to find out how many bytes Am79C974 AMD 13 ...
Page 148
... At the end of the DMA transaction, issue the IDLE command to the DMA engine MDL Based DMA Programming The following section outlines the procedure for execut- ing MDL based DMA operation: 1. Set up the MDL list 2. Use the programming sequence defined earlier for initiating a SCSI DMA transfer Am79C974 18681A/1-30 ...
Page 149
... DMA transaction. Each register address is represented by the PCI Con- figuration Base Address (B) and its corresponding offset value. The Base address for the Am79C974 is stored at register address (10h) in the PCI configuration space. Table 6. The DMA Registers Register Description ...
Page 150
... AMD DMA Scatter-Gather Mechanism The Am79C974 contains a scatter-gather translation mechanism which facilitates faster data transfers. This feature uses a Memory Descriptor List (a list of contigu- ous physical memory addresses) which is stored in sys- tem memory. Use of the Memory Descriptor List allows a single SCSI transfer to be read from (or written to) non- contiguous physical memory locations ...
Page 151
... When the first entry in the MDL in read (page frame address #1), the WMAC register is incremented to point to the next page entry (page frame address #2). 2. Issue the Start DMA Command. The Am79C974 reads the page frame address (bits 31:12) from the 31 SPA ...
Page 152
... Count into the SCSI Start Transfer Count Register and the DMA Starting Transfer Count Register. 8. Reprogram the DMA Starting Physical Address Register ((B)+48h) to the Physical Address of the next Scatter-Gather element. 9. Repeat steps 4–8 until the Scatter-Gather list is completed. Am79C974 4K Page #n Data 18681A/1-34 ...
Page 153
... C1 – C9 are decoupling capacitors. Figure E-5. Decoupling Capacitor Placement Am79C974 AMD 18681A/1-67 19 ...