am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 43

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Ethernet Controller
Buffer Management Unit (BMU)
The buffer management unit is a micro-coded state ma-
chine which implements the initialization procedure and
manages the descriptors and buffers. The buffer man-
agement unit operates at half the speed of the
CLK input.
Initialization
Am79C974 initialization includes the reading of the in-
itialization block in memory to obtain the operating pa-
rameters. The initialization block is read when the INIT
bit in CSR0 is set. The INIT bit should be set before or
concurrent with the STRT bit to insure correct operation.
Two DWORDs are read during each period of bus ma-
stership. When SSIZE32 = 1 (BCR20, bit 8), this results
in a total of 4 arbitration cycles (3 arbitration cycles if
SSIZE32 = 0). Once the initialization block has been
completely read in and internal registers have been up-
dated, IDON will be set in CSR0, and an interrupt gener-
ated (if IENA is set). At this point, the BMU knows where
the receive and transmit descriptor rings and hence,
normal network operations will begin.
The Am79C974 controller obtains the start address of
the Initialization Block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most signifi-
cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The block contains the
user defined conditions for Am79C974 operation, to-
gether with the base addresses and length information
of the transmit and receive descriptor rings.
There is an alternative method to initialize the
Am79C974 controller. Instead of initialization via the in-
itialization block in memory, data can be written directly
into the appropriate registers. Either method may be
used at the discretion of the programmer. If the registers
are written to directly, the INIT bit must not be set, or the
initialization block will be read in, thus overwriting the
previously written information. Please refer to Appendix
C for details on this alternative method.
If initialization is done by writing directly to registers, the
Polling Interval register (CSR47) must be initialized in
addition to those registers that can be loaded automati-
cally from the initialization block.
Re-Initialization
The transmitter and receiver sections of the Am79C974
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
states of the transmitter and receiver are monitored by
the host through CSR0 (RXON, TXON bits). The
Am79C974 controller should be reinitialized if the trans-
mitter and/or the receiver were not turned on during the
original initialization, and it was subsequently required
to activate them or if either section was shut off due to
P R E L I M I N A R Y
Am79C974
the detection of certain error conditions (MERR, UFLO,
TX BUFF error).
Reinitialization may be done via the initialization block or
by setting the STOP bit in CSR0, followed by writing to
CSR15, and then setting the START bit in CSR0. Note
that this form of restart will not perform the same in the
Am79C974 controller as in the LANCE. In particular,
upon restart, the Am79C974 controller reloads the
transmit and receive descriptor pointers with their re-
spective base addresses. This means that the software
must clear the descriptor own bits and reset its descrip-
tor ring pointers before the restart of the Am79C974
controller. The reload of descriptor base addresses is
performed in the LANCE only after initialization, so a re-
start of the LANCE without initialization leaves the
LANCE pointing at the same descriptor locations as be-
fore the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4
DWORDs, or 16 bytes, when SSIZE32 = 1. The size of a
message descriptor entry is 4 words, or 8 bytes, when
SSIZE32 = 0.
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the Am79C974 controller reads the user-de-
fined base address for the transmit and receive descrip-
tor rings, as well as the number of entries contained in
the descriptor rings. Descriptor ring base addresses
must be on a 16-byte boundary when SSIZE32=1, and
8-byte boundary when SSIZE=0. A maximum of 128 (or
512, depending upon the value of SSIZE32) ring entries
is allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. However, the
ring lengths can be set beyond this range (up to 65535)
by writing the transmit and receive ring length registers
(CSR76, CSR78) directly.
Each ring entry contains the following information:
1. The address of the actual message data buffer in
2. The length of the message buffer
3. Status information indicating the condition of the
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
Am79C974 controller or the host. The OWN bit within
the descriptor status information, either TMD or RMD
(see section on TMD or RMD), is used for this purpose.
OWN = “1” signifies that the Am79C974 controller cur-
user or host memory
buffer
AMD
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