am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 81

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

The Fast SCSI Block
The functionality of the SCSI block is described in the
following section. Topics to be covered are:
SCSI Block ID
The Am79C974 contains a SCSI Block ID code which is
stored in the MSB of the Current Transfer Count Regis-
ter. The code reflects the chip’s revision level and family
code. This 8-bit code may be read when the following
conditions are true.
The part-unique ID code in Register ((B)+38h) will read
as follows:
SCSI FIFO Threshold
The threshold value for the SCSI FIFO is two bytes (one
word). When this threshold is reached, the SCSI block
will indicate to the DMA engine that it is capable of re-
ceiving or sending data bytes.
Data Transmission
Data transmission rates will vary from system to system,
depending on the number of devices configured on the
SCSI bus, as well as the transfer rates that each individ-
ual device is capable of sustaining.
Transfer rates for the Am79C974 are controlled by the
FASTSCSI and FASTCLK bits in Control Register
Three, as well by the Extended Timing Feature in Con-
trol Register One.
To achieve 10 Mbyte/s transmission rates, the following
conditions must be true:
Bit 7
After power up or a chip reset has occurred
Before the Current Transfer Counter ((B)+38h) is
0
Illegal command code issued
The target disconnects from the SCSI bus
SCSI bus service request
Successful completion of a command
The Am79C974 has been reselected
SCSI Block ID
SCSI FIFO Threshold
Data Transmission
REQ/ACK Control
Parity
Reset Levels
loaded
A 40 MHz clock (50% duty cycle) must be supplied
to SCSICLK.
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
1
P R E L I M I N A R Y
Bit 0
0
Am79C974
The FASTCLK and FASTSCSI bits in Control Register
Three modify the SCSI state machine to produce both
FAST and Normal SCSI timings. Synchronous data
transmission rates are dependent on the input clock fre-
quency selected, as well as the transfer period.
Bits 4:0 in the Synchronous Transfer Period Register
((B)+18h) specify the period for synchronous data trans-
fers. For programming information, refer to the Techni-
cal Manual.
REQ/ACK Control
The assertion and deassertion time for the REQ and
ACK signals may be controlled via the Synchronous Off-
set Register ((B)+1Ch). Bits 7:6 control REQ/ACK
deassertion delay with respect to the time that data is
valid, while bits 5:4 control REQ/ACK assertion delay.
The deassertion for REQ/ACK may be moved ahead .5
clock cycles, or it may be delayed for up to 1.5 clock cy-
cles. Deassertion delay options depend on the status of
the FASTCLK bit in Control Register Three. Assertion
delay for REQ/ACK can vary from 0 to 1.5 clock cycles.
Parity
Parity on the SCSI bus is such that the total number of
logical ones on data bus including the parity bit must be
odd. Parity checking features are implemented via two
bits in the Status Register and Control Register One.
Parity checking can be implemented on data flowing in
from the SCSI bus. Parity is always generated internally
by the Am79C974 for data moving onto the SCSI bus.
Parity Checking on the SCSI Bus
The Parity Error Reporting Bit (Bit 4, Control Register
One) enables parity checking on all incoming bytes from
the SCSI bus. This feature is cleared to ‘0’ by a hardware
reset.
Parity Status
Parity From
The target must be able to sustain Fast SCSI
timings.
Bits 3 (FASTCLK) and 4 (FASTSCSI) in Control
Register Three must be set to ‘1.’
The lower three bits of Register ((B)+24h), the
Clock Conversion Factor Register must be
programmed to ‘000.’
The lower 5 bits of the Synchronous Transfer
Period Register ((B)+18h) must be set to a value
of ‘04h.’
Feature
SCSI
Parity Error
Parity Error
Bit Name
Reporting
Bit #
4
5
((B)+20h)
((B)+10h)
Register
Reg One
Register
Control
Status
AMD
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