am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 149

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
Command Register (CMD)
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Address (B)+40h, LSB
DIR:
Data transfer direction bit.
INTE_D:
DMA transfer active interrupt bit.
Register Acronym
CMD
STC
SPA
WBC
WAC
STATUS
SMDLA
WMAC
DIR
7
CMD1
0
0
1
1
INTE_D
6
INTE_P
CMD0
5
0
1
0
1
MDL
4
Addr (Hex)
(B)+4C
(B)+5C
(B)+40
(B)+44
(B)+48
(B)+50
(B)+54
(B)+58
Reserved Reserved
Command
3
ABORT
START
BLAST
IDLE
2
Register Description
Command
Starting Transfer Count
Starting Physical Address
Working Byte Counter
Working Address Counter
Status Register
Starting Memory Descriptor List (MDL) Address
Working MDL Counter
READ/WRITE
Table 6. The DMA Registers
Description
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
Terminates the current DMA transfer. The DMA engine
should be restored to the ‘IDLE’ state following execution of
this command.
Note: This is only valid after a ‘START’ command is issued.
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note: This command should be issued only after all other
control bits have been initialized.
CMD1
1
A M E N D M E N T
(bits 31:8 reserved, bits 7:0 used)
CMD0
0
Am79C974
(bits 31:8 reserved, bits 7:0 used)
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Con-
figuration Base Address (B) and its corresponding offset
value. The Base address for the Am79C974 is stored at
register address (10h) in the PCI configuration space.
INTE_P:
Page transfer active interrupt bit.
MDL:
Memory Descriptor List (MDL) SPA enable bit.
RESERVED:
Reserved for future expansion. The zero value must be
written in these bits.
CMD1-0:
These two bits are encoded to represent four com-
mands: IDLE, BLAST, START, and ABORT.
(bits 31:24 reserved, bits 23:0 used)
(bits 31:0 used)
(bits 31:0 used)
AMD
Type
R/W
R/W
R/W
R/W
R
R
R
R
15