am79c864a Advanced Micro Devices, am79c864a Datasheet
am79c864a
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am79c864a Summary of contents
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... PRELIMINARY Am79C864A Physical Layer Controller With Scrambler (PLC-S) DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Implements ANSI standard Stream Cipher Scrambling/Descrambling Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and removal On-chip Link Error Monitor (LEM) and Link ...
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AMD PLC-S chip during Link Confidence Test and after the link has been formed, to detect a noisy link. The PLC-S contains a Line State Machine for detecting received line states and a Data Stream Generator for transmitting the various ...
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... Elasticity LM Buffer/ Local Smoother Lbmux Decoder Line State Machine Built-in Repeat Self Test Filter Encoder Data Stream Generator Am79C864A AMD Bypass Scrub Receive Data Mux Mux Output RX 11 Idles TX 11 Remote Transmit Loopback Mux Data Input ...
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AMD DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION PLC-S BLOCK DIAGRAM PLC-S CORE BLOCK DIAGRAM TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Am79C864A AMD ...
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AMD CONNECTION DIAGRAM 120-Pin PQR (Top View INT 2 3 NPADDR4 4 NPADDR3 5 NPADDR2 6 NPADDR1 NPADDR0 TDAT0 10 11 TDAT1 12 TDAT2 13 TDAT3 TDAT4 ...
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... TX5 82 LSR2 TX4 83 VDD VDD 84 VSS VSS 85 LSR1 TX3 86 LSR0 TX2 87 VSS TX1 88 ULSB TX0 VSS 89 TXPAR VDD 90 VDD Am79C864A AMD Pin Number Pin Name 91 VSS 92 VSS RST 93 94 NP0 95 NP1 96 NP2 97 VDD 98 VSS 99 NP3 100 NP4 101 NP5 102 NP6 ...
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AMD LOGIC SYMBOL BCLK NPCLK RSCLK LSCLK RDAT 4–0 TX 9–0 TXPAR CS NPRW NPADDR 4–0 RST SDO TEST 2–0 RRSCLK SCRM ENCOFF VDD VSS 3-10 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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... PACKAGE TYPE K = 120-Plastic Quad Flatpack in TapePak Not Applicable Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C864A AMD (PQJ120) (PQR120) Valid Combinations 3-11 ...
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AMD PIN DESCRIPTION Clock Signals BCLK Byte Clock (Input) BCLK is a 12.5 MHz clock used by the PLC-S to clock most internal operations, clock RX 9–0 to the MAC device and, along with LSCLK, latch TX 9–0 ...
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... The different operating modes are as follows: TEST 2– Scan Input Am79C864A AMD Mode of Device Operation Normal Operating Mode Normal Operating Mode Factory Test Mode (Counter Segmentation Test) Boundary Scan Serial Test Mode ...
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AMD RRSCLK Reserved (Input) This pin should be connected to VSS. Control and Status Signals EBFERR Elasticity Buffer Error (Output, Active High) EBFERR indicates when an overflow or underflow con- dition occurs in the Elasticity Buffer. ENCOFF Encoder Off (Input, ...
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... PLC-S during a write cycle. The PLC-S will not attempt to write to a selected register more than once until the CS signal has been deasserted. Thus, to ac- complish back to back writes, the Node Processor must deassert the CS signal before attempting the second write. Am79C864A AMD 3-15 ...
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AMD NPRW = NPRW = NPRW = 1 Read1 Drive NP Read2 Read4 Read5 Figure 1. Node Processor Interface State Machine 3-16 The ...
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... The PLC_CNTRL_A register bit assignments are listed in Table 2. read/write read/write read/write read/write write only (Note 2) write only (Note 3) read only read only read only read only read only read only read only read only (Note 4) read only (Note 4) read only (Note 4) read only (Note 4) Am79C864A AMD 3-17 ...
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AMD Addr (Hex) NOISE TNE-16 TPC-16 REQ TIMER BIT BIT SCRUB Bit Name Definition 15 Reserved 14 NOISE_TIMER The NOISE_TIMER bit allows the noise timing function of the PCM to be used when ...
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... BIST will restart. For more detail, refer to pages 30 and 42 . Reset PLC-S before setting this bit Table 2. PLC_CNTRL_A (continued) REQ_SCRUB SET RESET RESET SET Am79C864A AMD RX 9–0 IDLE TX 9–0 RDAT 4–0 RDAT 4–0 3-19 ...
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AMD PLC-S Control Register B (PLC_CNTRL_B) PLC_CNTRL_B has address 01 (hex readable and writeable. All bits of this register are cleared with the as- sertion of RST. PLC_CNTRL_B contains signals and re- quests to direct the process of ...
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... The PCM asserts Transmit PDR. This assumes that Protocol Data Units (PDUs) will be input at TX(9–0). The PCM asserts Transmit Idle. This causes the PLC-S to source Idle symbols. The PCM asserts Transmit PDR and sets up a remote loopback path in the PLC-S. Am79C864A AMD 3-21 ...
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AMD Bit Name Definition 01–00 PCM_CNTRL PCM_CNTRL controls the PCM state machine. When set to a value other than zero, it will cause the PCM to immediately make a transition to the BREAK, TRACE or OFF state. The transition to ...
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... The PLC_CNTRL_C register bit assignments are listed in Table 4. PLC_CNTRL_C SDON_ SDON_ FOTOFF_ FOTOFF_ SDON_ TIMER TIMER CTRL CTRL ENABLE Table 4. PLC_CNTRL_C Am79C864A AMD SDOFF_ CIPHER_ RESERVED ENABLE LPBCK 15535B-8 CIPHER_ ENABLE 0 3-23 ...
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AMD PLC-S Status Register A (PLC_STATUS_A) PLC_STATUS_A has address 10 (hex read-only used to report status information to the Node Proc- essor about the Line State Machine (LSM). Addr (Hex) 10 REVISION_ID ...
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... Name REMOVED INSERT_SCRUB REMOVE_SCRUB INSERTED Name PC0 (OFF) PC1 (BREAK) PC2 (TRACE) PC3 (CONNECT) PC4 (NEXT) PC5 (SIGNAL) PC6 (JOIN) PC7 (VERIFY) PC8 (ACTIVE) PC9 (MAINT) Reserved Am79C864A AMD BREAK BREAK BREAK RCF TCF REASON REASON REASON 15535B-11 ...
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AMD Bit Name Definition 06 PCM_SIGNALING PCM_SIGNALING is a flag from the PCM indicating that the XMIT_VECTOR register has been written. The XMIT_VECTOR and VECTOR_LENGTH registers cannot be written when this flag is set. 05 LSF The Line State Flag ...
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... The Link Confidence Test (LCT) Time register (LC_LENGTH) has address 0B (hex). This register specifies the time duration of the LCT and limits the du- ration of loopback to prevent deadlock. It has a recom- mended value (F676 hex in 2’s complement) Am79C864A AMD 16 times 2 times 80 ns) units. It ...
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AMD for the short LCT. For medium LCT, it has a recom- mended value of 500 ms (A0A2 hex in 2’s complement). Scrub Time Register (T_SCRUB) The Scrub Time (T_SCRUB) register has address 0C (hex). It has a recommended value ...
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... BER, e.g. due to a marginal link quality, link degradation or connector unplugging. In addition to the counter, the PLC-S also contains logic to detect link error events. Link error events are defined in Table 12. Am79C864A AMD Minimum Idle Occurrence Count 0000 1 ...
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AMD Link Error Event Threshold Register (LE_THRESHOLD) The Link Error Event Threshold register has address 05 (hex readable and writeable and is cleared on the assertion of RST. Bits 7 through 0 of this register contain a value ...
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... This bit will not be set if ENA_PAR_CHK bit in PLC_CNTRL_A register is cleared INTR-EVENT EBUF TNE TPC PCM PCM PHYINV ERR EXPIRED EXPIRED ENABLED BREAK Table 10. INTR_EVENT Register Am79C864A AMD SELF TRACE PCM LS PARITY TEST PROP CODE MATCH ERR 15535B-12 3-31 ...
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AMD Interrupt Mask Register (INTR_MASK) The Interrupt Mask Register (INTR_MASK) has ad- dress 02 (hex readable and writeable. It allows the disabling of interrupts caused by specific events. The INTR_MASK contains a bit that corresponds to each bit ...
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... CMT. Fundamental to this task is the management of a connection between two physical attachments (PHYs) in adjacent stations the job of the PCM state machines in both stations to cooperate in forming a connection between the two PHYs within the rules established by the Connection Management. Am79C864A AMD When the LINK_ERR_CTR Exceptions ...
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AMD The FDDI SMT ANSI Standard defines the following types of physical attachment: A. Dual ring PHY entity connected to Primary Ring In, Secondary Ring Out B. Dual ring PHY entity connected to Secondary Ring In, Primary Ring Out M. ...
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... BREAK_REASON field in the PLC_STATUS_B register. Typically, three bits are written into the XMIT_VECTOR register in the beginning. After they are received, the re- ceived bits are read by the node processor to know the connection type. Then the node processor decides if the Am79C864A AMD 3-35 ...
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AMD connection is acceptable and flags the next bit. On re- ceipt of the corresponding bit from the neighbor, the node processor decides the length of the Link Confi- dence Test and communicates it through the next two bits. On ...
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... PCM state machine will not re–start the con- nection process. The PCI state machine remains in the REMOVE_SCRUB state for T_SCRUB length of time and then enters the REMOVED state. Note that if the connection is broken while the PCI state machine is in the INSERT_SCRUB state, scrubbing will Am79C864A AMD 3-37 ...
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AMD continue for T_SCRUB length of time and then enter the REMOVED state. PCI Operation for Class S Type Station For a Class S type station, the PCI Operation is same as above with one exception. Normally, for a Non-Class ...
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... Elasticity Buffer error (buffer overflow or underflow). PHY_INVALID takes precedence over Violation Elasticity Buffer error occurs while the Current Line State is Quiet, PHY_INVALID (1F in hex) is given to MAC. The symbol decoding is shown in Table 15. Am79C864A AMD Insert Scrub PCI1 Halt, Master, or Noise ...
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AMD Table 15. 4B/5B Decoding of Data Symbol Encoded Input ...
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... When there is not a match, the output data is the scrambled data XORed with the random generator’s output. The random gen- S_Data = A erator is open loop the random Am79C864A AMD Table 17. Line States Data H 00000000000 00000000000 11111111111 11111111111 ...
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AMD Using the Stream Cipher Scrambler The system has access to the scrambler and descrambler through a pin and a register. Pin 41 (SCRM) and bit 0 (CIPHER_ENABLE) PLC_CNTRL_C enable the scrambler. SCRM and Table 18. Stream Cipher Enable SCRM ...
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... The Scrub MUX selects its input from either constant Idle symbol pairs or the output of the BYPASS_MUX. When the REQ_SCRUB bit in the PLC_CNTRL_A reg- ister is set while the PCM is in the MAINT state, or when CONFIG_CNTRL bits is set in the PLC_CNTRL_B Am79C864A AMD bit is set ...
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AMD register, the PCI is in the INSERT_SCRUB or REMOVE_SCRUB state, the output of the Scrub MUX is Idle symbols. Otherwise transmit data from the BYPASS_MUX is placed on the Receive Data Output Latch. This MUX is used when the ...
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... Table 19. Boundary Scan Chain Order Pin RDAT0 to RDAT4 FOTOFF TDAT4 to TDAT0 by reading the TX0 to TX9 TXPAR RXPAR RX9 to RX0 Am79C864A AMD Type Input Input Output Output Output Input Input Input Output Output Output Output Output 3-45 ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature . . . . . . . . . . . . . . . Supply Voltage Referenced ...
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... Min BCLK Periods Am79C864A AMD Max Unit ...
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AMD KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS NPCLK BCLK 13 LSCLK RSCLK 3-48 The SUPERNET 2 Family for FDDI 1994 Data Book WAVEFORM INPUTS OUTPUTS Must be Will be ...
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... SWITCHING WAVEFORMS BCLK LPBCK FOTOFF, SCANO LSR, ULSB, EBFERR 34 SDO TEST2-0 ENCOFF PLC-S Misc Signals Timing Diagram Am79C864A AMD 2 39 15535B-19 3-49 ...
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AMD SWITCHING WAVEFORMS 4 NPCLK NPRW 17 16 NPADDR NP INT RST 3-50 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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... SWITCHING WAVEFORMS 10 RSCLK 30 RDAT BCLK RX RXPAR 7 LSCLK 28 TX TXPAR 36 TDAT PLC-S Data Interface Timing Diagram Am79C864A AMD 29 15535B-22 3-51 ...
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AMD SWITCHING TEST CIRCUIT From Output Under Test Note for all bidirectional or output pins. L 3-52 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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... SWITCHING TEST WAVEFORMS 3.0 V 1.5 V 0.0 V 1.5 V Enabled Input Bus In High- Impedance State Input Bus Valid Input Waveform Test Points Output Bus In High- Impedance State Output Bus Valid Output Waveform Test Points Am79C864A AMD 1.5 V 15535B-24 1.5 V 1.5 V 15535B-25 3-53 ...