am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 11

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

NP 15–0
Node Processor Data Bus (Input/Output, Three
State)
The NP 15–0 bus is a sixteen bit bi-directional, three-
state data bus used to exchange data between the
PLC-S and the Node Processor.
NPRW
Node Processor Read/Write (Input)
The NPRW signal indicates whether the current bus cy-
cle is a read (NPRW = 1) or a write (NPRW = 0) cycle.
RST
Reset (Input, Active Low, Asynchronous)
The RST signal provides a means of initializing the
PLC-S on power up. When asserted, the Reset causes
the following:
Once RST is asserted low, it must remain asserted for at
least twenty NPCLK cycles. When it is deasserted the
PLC-S is ready to begin its normal operation.
Assertion and deassertion are asynchronous. A warm
reset (assertion of RST after the device is in operation)
will cause device outputs to be unpredictable until the
device is initialized.
PDT and PDR Interface Signals
LPBCK
Loopback (Output, Active Low)
The LPBCK signal controls the receive multiplexer in the
PDR device. If LPBCK= 0, the MUX selects its input
from the PDT. If LPBCK = 1, the MUX selects its input
from the Fiber Optic Receiver.
FOTOFF
Fiber Optic Transmitter Off (Output, Active Low)
The FOTOFF signal, when asserted, causes the PDT to
transmit Quiet symbols. This signal is asserted
whenever:
The various state machines are initialized:
LSM-NOT ACTIVE, PCM-OFF, PCI-REMOVED,
Repeat Filter on REPEAT, Node Processor
Interface-NOT ACTIVE.
All writable registers are cleared and all
registers that are cleared on a read are cleared.
Built-in Self Test – OFF
The Fiber Optic Transmitter Off (FOTOFF) signal
is asserted, Quiet Symbols are transmitted on
TDAT, and TX is looped back onto RX.
The FOT_OFF bit, LOOPBACK bit,
EB_LOC_LOOP bit, LM_LOC_LOOP bit in the
PLC_CNTRL_A register (or) CIPHER_LPBCK bit
in PLC_CNTRL_C register is set.
P R E L I M I N A R Y
Am79C864A
SDO
Signal Detect (Input, Active High)
The SDO signal is output by the PDR to indicate whether
the Fiber Optic Receiver is detecting an optical signal
above its threshold. The inverted value of this signal is
held in the PLC_STATUS_A register, and the LSDO bit
in the INTR_EVENT register is set when SDO is
asserted.
Test Signals
PTSTO
Parametric Test Output (Output)
This is an internal parametric test output signal. This pin
should be left unconnected.
SCANO
Scan Output (Output)
The SCANO signal is used as an output of the scan
chain when the PLC-S is in Boundary Scan Serial Test
Mode.
TEST 2–0
PLC-S Test Mode (Input)
The three TEST 2–0 input pins are used to select be-
tween normal operating mode and three different test
modes. The different operating modes are as follows:
0 0 0
0 1 X
0 0 1
1 0 Scan Input
1 1 0
1 1 1
The MAINT_LS field in the PLC_CNTRL_B
register equal Transmit QUIET and the PCM is
in the MAINT state and FOTOFF assertion timer
expires, if enabled.
The Physical Connection Management logic has
set LS_REQUEST = Transmit QUIET Line State
and FOTOFF assertion timer expires, if enabled.
Built-in Self Test is active.
TEST 2–0
Mode of Device Operation
Normal Operating Mode
Normal Operating Mode
Factory Test Mode
(Counter Segmentation Test)
Boundary Scan Serial
Test Mode
Boundary Scan Parallel
Test Mode
All output pins except
PTSTO are High
Impedance
AMD
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