am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 34

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

connection is acceptable and flags the next bit. On re-
ceipt of the corresponding bit from the neighbor, the
node processor decides the length of the Link Confi-
dence Test and communicates it through the next two
bits. On receipt of the corresponding bits from the neigh-
bor, the node processor communicates if it wants to per-
form LCT through the MAC. After receipt of
corresponding bit from the neighbor, the LCT is per-
formed. If the length of the LCT is longer, then the node
processor will set the LONG bit in the PLC_CNTRL_B
register. If LONG bit is set, the node processor has to is-
sue a PC_SIGNAL command to progress the sequence
and communicate the status of LCT in the next bit.
On receipt of the corresponding bit from the neighbor,
the MAC LOOPBACK bit is sent. On receipt of MAC
LOOPBACK bit from the neighbor, the MAC LOOP-
BACK is performed based on the bit information. Once
the MAC LOOPBACK is finished, the last bit is commu-
nicated indicating if the MAC output is going to be con-
nected to this PHY.
After the LCT is completed (i.e. after LC_LENGTH, or
after Halt or Master Line State is received) the
PCM_CODE interrupt is set. If the Node Processor de-
cides to transmit more signaling bits it should load the
VECTOR_LENGTH with a new value of n and then the
XMIT_VECTOR register with the bit pattern to be trans-
mitted. The PCM again starts transmitting these bits and
alternates between NEXT and SIGNAL states until all
bits are transmitted upon which the PCM_CODE inter-
rupt is set again.
This sequence continues until all the bits are transmitted
and the Node Processor writes PC_JOIN in the
PLC_CNTRL_B register. The PCM then leaves the
NEXT state and enters the JOIN state. Setting these bits
has no effect when the PCM is not in the NEXT state or
when the PCM_SIGNALING bit is set. However, if this
3-36
AMD
The SUPERNET 2 Family for FDDI 1994 Data Book
P R E L I M I N A R Y
bit is set even though LCT is not finished yet, then LCT
will be aborted and the PCM join sequence will be
initiated.
Noise Detection Mechanism
The TNE Timer in the PCM times the period between the
receptions of the Idle Line State. This timer is loaded
with the NS_MAX parameter when Line State Machine
leaves the Idle Line State. The TNE Timer keeps count-
ing the Noise until Idle Line State is again detected.
While in the ACTIVE state if this timer expires then the
PCM will break the link and transition to the BREAK
state. In the ACTIVE state the TNE Timer starts count-
ing noise only after LSF is set. If PC_Trace is set and the
TNE Timer expires in the same cycle then the transition
to the TRACE state is taken. This timer is ignored in all
the PCM states except the ACTIVE state.
Noise in MAINT State
If the NOISE_TIMER bit in the PLC_CNTRL_A register
is not set, then the Node Processor can write the TNE
Timer if the PCM is in MAINT state. If the NOISE_TIM-
ER bit is set, then the TNE Timer is used in the MAINT
state to time the Noise as described above. If the TNE
Timer expires, then the TNE_EXPIRED bit in the
INTR_EVENT register is set.
Operation in TRACE State
In the ACTIVE state if Trace Propagation (i.e., receipt of
Master Line State) is detected then the TRACE_PROP
interrupt is set. In the ACTIVE state if PC_Trace is re-
ceived and a transition is made to the TRACE state then
the station remains inserted, Master Line State is
sourced on the TDAT(4–0) port, and no scrubbing is
performed. Again in this state if Master Line State is de-
tected, the TRACE_PROP interrupt is set. If Quiet Line
State or Halt Line State is detected, then the
SELF_TEST interrupt is set.