am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 42

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

register,
REMOVE_SCRUB state, the output of the Scrub MUX
is Idle symbols. Otherwise transmit data from the
BYPASS_MUX is placed on the Receive Data Output
Latch.
This MUX is used when the PLC-S operates in a Con-
centrator. When a port in a Concentrator is connecting
to an end station, Idle symbols are output on RX 9–0 so
as to scrub the ring before the station starts putting data
onto the ring. When a port in a Concentrator is not con-
nected to another station, the port is bypassed by
routing TX back out on RX.
Test Data MUX
In normal operating mode the Test Data MUX sends the
data output by the Encoder to the Transmit Data Output
Latch.
When the built-in self test is running the Test Data MUX
selects the input from the BIST block. This is how BIST
inserts pseudo-random test data into the loop it forms
with the transmit and receive data paths. This point was
chosen to inject test data because it was desired to
avoid sending the test data through the Repeat Filter
and the Data Stream Generator. Since both of these
logic blocks act as filters, coverage of stuck-at faults in
other parts of the chip would be reduced if data from
these blocks rather than random test data were used.
Data Input/Output
The PLC-S contains four ports for receiving and trans-
mitting network data: Receive Data Input, Receive Data
Output, Transmit Data Input, and Transmit Data Output.
The signal timing for these ports is detailed in the
Switching Characteristics and Switching Waveforms
chapters of this document.
Receive Data Input
RDAT is a five-bit (symbol wide) data bus going from the
PDR chip to the PLC-S. RSCLK is also input from the
PDR chip and is divided by two to get a recovered byte
clock. RDAT is latched on each rising and falling edge of
the recovered byte clock. Following the rising edge of
the recovered byte clock, the five bits (symbol) just
latched, plus the five bits (symbol) latched by the previ-
ous falling edge recovered byte clock edge, are used in-
ternally in the PLC-S. All data paths inside the PLC-S
are 10 bits (two symbols) wide.
Receive Data Output
RX is a ten-bit (symbol pair wide) data bus going from
the PLC-S to the a MAC device in a Single Attachment
Station (SAS). In the case of a Concentrator or a Dual
Attachment Station (DAS), RX may also go to another
PLC-S. Data is latched inside the PLC-S on each rising
edge of BCLK and is available to the MAC device shortly
after this clock edge.
3-44
AMD
the PCI is in the INSERT_SCRUB or
The SUPERNET 2 Family for FDDI 1994 Data Book
P R E L I M I N A R Y
Transmit Data Input
TX is a ten-bit (symbol pair wide) data bus going from
the MAC device (or in a Concentrator/DAS, from an-
other PLC to the PLC-S. The data is latched by the fall-
ing edge of LSCLK that precedes the rising edge of
BCLK. Then it is latched again by that rising edge of
BCLK. Assuming no skew between LSCLK and BCLK,
this effectively adds a one half LSCLK period to the hold
time provided on TX. Any amount by which BCLK trails
LSCLK will subtract from the hold time provided.
Transmit Data Output
TDAT is a five-bit (symbol wide) data bus going from the
PLC-S to the PDT. The ten bit wide internal data bus is
latched initially by the PLC-S by each rising edge of
BCLK. Bits nine through five are sent on the rising edge
of LSCLK following the rising edge of BCLK. Bits four
through zero are then sent on the rising edge of LSCLK
following the falling edge of BCLK. Data are available to
the PDT shortly after each rising edge of LSCLK.
Built In Self Test (BIST)
The Built In Self Test block contains logic to run the
PLC-S Built In Self Test and also contains control logic
for the chip’s Counter Segmentation Test Mode and
Boundary Scan Test Mode.
BIST Operation
The bulk of the PLC-S data path and state machine logic
is tested by BIST. It remains passive during normal chip
operation. Under test mode, BIST tests the chip, and re-
turns a signature which verifies the functioning of the
chip’s logic with a high degree of certainty. Since BIST
sits right on the silicon with the rest of the chip, it has the
advantage of the optimum observability location: inside
the chip.
BIST tests the PLC-S by circulating pseudo random
data throughout the chip. The various subcircuits within
the chip are observed as they respond to these data,
and a signature based upon their behavior is generated.
This signature may be checked against the known cor-
rect signature, to verify the functioning of the chip. A sin-
gle fault in the chip, as long as it is covered by BIST, will
cause a different signature to be generated.
The majority of the logic blocks of the PLC-S sit directly
on the chip’s data path. These blocks are easily tested
by placing pseudo random vectors, generated by the
Linear Feedback Shift Register (LSFR), on the data
paths, and observing the behavior of the blocks with the
Signature Generator.
With this method, data from LFSR are input by the
Transmit Data Output latch lines via the Test Data Mux
(see Block Diagram on page 2). The test data are looped
back onto the receive data path via the EB Local Loop-
back MUX. The test data traverse the entire receive data