s71pl127j04bfwtz3 Meet Spansion Inc., s71pl127j04bfwtz3 Datasheet - Page 20

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s71pl127j04bfwtz3

Manufacturer Part Number
s71pl127j04bfwtz3
Description
Stacked Multi-chip Product Mcp Flash Memory And Ram With 32 Megabit 2m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory And 16/8/4 Megabit 1m/512k/256k X 16-bit Pseudo Static Ram Or 8/4 Megabit Cmos Static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
8. Revision History
20
Revision A (May 3, 2004)
Revision A1 (May 6, 2004)
Features
Connection Diagrams
Ordering Information
Revision A2 (May 11, 2004)
General Description
Revision A3 (June 16, 2004)
Ordering Information
Revision A4 (July 16, 2004)
Global
32 Mb Flash Memory
64 Mb Flash Memory
128 Mb Flash Memory
256 Mb Flash Memory
Connection Diagrams
S71PL032J Valid Combinations
S71PL064J Valid Combinations
S71PL127J Valid Combinations
S71PL254J Valid Combinations
Section
Initial release
Corrected the high performance access times.
Added reference points on all diagrams.
Corrected package types.
Corrected the description of product family to Page Mode Flash memory.
Corrected the tables to reflect accurate device configurations.
Corrected the Valid Combinations tables to reflect accurate device configurations.
Global Change of FASL to Spansion.
Global change to remove space between M and Mb callouts.
Replaced “S71PL032J08-07” with “S71PL032J08-0B”.
Replaced “S71PL032JA0” with “S71PL032JA0-07”.
Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”.
Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056.
Replaced “S71PL064J08-0K” with “S71PL064J08-0B”.
Replaced “S71PL064J08-0P” with “S71PL064J08-0U”.
Deleted “S71PL064J80-05” row.
Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”.
Replaced “S71PL064JA0-0Z” with
Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056.
Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064.
Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”.
Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064.
Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”.
In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”.
Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084.
Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084.
Updated pins D8, D9, and L5.
Added notes 2 and 3 to drawing.
Updated pins D8 and D9.
Added Note 2 to drawing.
Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to “SRAM2” (4 changes
made in table).
Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to pSRAM3 /70”.
Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”. Merged previous place
holder with cell above.
In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/70”.
In Package Modifier/Model Number changed all instances of “stet” to “07”.
Added row to BAW Package and Temperature sections with the following content: S71PL064JB0;
07; 65 (previously inclusive); pSRAM1/70.
Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4 instances).
Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70.
Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70.
Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70.
S71PL-J Based MCPs
D a t a
S h e e t
Description
S71PL-J_00_B5 July 17, 2007

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