m36p0r9060e0 STMicroelectronics, m36p0r9060e0 Datasheet - Page 15

• Manufacturer Part Number: m36p0r9060e0
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: STMicroelectronics

M36P0R9060E0
Table 2.
1. X = Don't care
2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
4. The DPD
5. WAIT signal polarity is configured using the Set Configuration Register command. See the M58PRxxxJ datasheet for
6. L
7. ECR15 has to be set to ‘1’ for the Flash memory device to enter Deep Power-Down.
8. Depends on G
9. If ECR15 is set to '0', the Flash memory device cannot enter the Deep Power-Down mode, even if DPD
10. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, V
Flash Bus
Read
Flash Bus
Write
Flash
Address
Latch
Flash Output
Disable
Flash
Standby
Flash Reset
Flash Deep
Power-Down
PSRAM Read
PSRAM Write
PSRAM Read
Configuration
Register
PSRAM
Standby
PSRAM Deep
Power-
Down
Operation
Standby and Deep Power-Down modes.
details.
Down mode.
F
can be tied to V
(10)
(3)
(2)
F
signal polarity depends on the value of the ECR14 bit.
Main operating modes
V
V
V
V
V
V
E
F
X
IH
IH
IL
IL
IL
IL
F
Any Flash memory mode is allowed.
IH
V
V
V
G
X V
X
X
X
Flash memory must be disabled
IH
IH
IL
if the valid address has been previously latched
F
W
V
V
V
X
X
X
IH
IH
IH
IL
F
V
V
V
IL
IL
L
X
X
X
X
IL
(6)
(6)
RP
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
F
(1)
asserted
asserted
asserted
asserted
asserted
asserted
asserted
DPD
de-
de-
de-
de-
de-
de-
F
(4)
(7)
(7)
(7)
(7)
(7)
(7)
(9)
WAIT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(5)
V
V
V
V
V
E
Any PSRAM mode is
IH
IH
IL
IL
IL
P
PSRAM must be
CR
V
V
V
V
X
IH
IL
IL
IL
disabled.
P
allowed.
G
V
V
X
X
X
IL
IL
P
W
V
V
V
X
X
IH
IH
IL
P
LB
UB
V
V
V
X
X
IL
IL
IL
P
P
,
X1(DIDR)
A19 A18
00(RCR)
10(BCR)
3 Functional description
X
X
IH
, during Deep Power-
X
X
Valid
Valid
F
A0-A17
is asserted.
A20-
A21
X
X
X
or Hi-Z
Data Out
Data Out
PSRAM
data out
PSRAM
PSRAM
data out
Data In
DQ15-
data in
Flash
Flash
Flash
DQ0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
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