scn68562 NXP Semiconductors, scn68562 Datasheet - Page 6

• Manufacturer Part Number: scn68562
• Description: Dual Universal Serial Communications Controller Duscc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PIN DESCRIPTION (Continued)
1995 May 01
TRxCA, TRxCB
CTSA/BN, LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GP12A/BN
DTCN
DONEN
RTSA/BN,
SYNOUTA/BN
V
GND
DD
Dual universal serial communications controller (DUSCC)
MNEMONIC
PIN NO.
32, 17
38, 11
34, 15
33, 16
35, 14
40, 9
44, 5
41, 8
DIP
23
27
48
24
TYPE
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1/2). The maximum external receiver/transmitter clock frequency is 4MHz.
Channel A (B) Clear-To-Send Input or Loop Control Output: Active-Low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
DUSCC detects logic level transitions on this input and can be programmed to generate an
interrupt when a transition occurs. When operating in the COP loop mode, this pin
becomes a loop control output which is asserted and negated by DUSCC commands.
This output provides the means of controlling external loop interface hardware to go on-line
and off-line without disturbing operation of the loop.
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-Low input, it acts as an enable for the receiver or can be
used as a general purpose input for the DCD function, the DUSCC detects logic level
transitions on this input and can be programmed to generate an interrupt when a transition
occurs. As an active-Low external sync input, it is used in COP modes to obtain character
synchronization without receipt of a SYN character. This mode can be used in disc or
tape controller applications or for the optional byte timing lead in X.21.
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-Low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-Low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to
-Send output, which can be asserted and negated under program control (see Detailed
Operation).
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-Low. For half-duplex single address DMA operation, this input indicates to the
DUSCC that the DMA controller has acquired the bus and that the requested bus cycle
(read receiver FIFO or load transmitter FIFO) is beginning. For full-duplex single address
DMA operation, this input indicates to the DUSCC that the DMA controller has acquired
the bus and that the requested read receiver FIFO bus cycle is beginning. Because the
state of this input can be read under program control, it can be used as a general purpose
input when not in single address DMA mode.
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-Low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the DUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
Device Transfer Complete: Active-Low. DTCN is asserted by the DMA controller to
indicate that the requested data transfer is complete.
Done: Active-Low, open-drain. See Detailed Operation for a description of the function of
this pin.
Channel A (B) Sync Detect or Request-to-Send: Active-Low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
+5V + 10% power input.
Signal and power ground input.
6
NAME AND FUNCTION
SCN68562
Product specification