scn2661 NXP Semiconductors, scn2661 Datasheet
scn2661
Available stocks
Related parts for scn2661
scn2661 Summary of contents
Page 1
... Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer. The SCN2661 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode ...
Page 2
... MAX, use the appropriate value specified under recommended operating conditions. 1994 Apr +5V +5% CC Commercial +70 C SCN2661BC1F28 SCN2661CC1F28 SCN2661AC1N28 SCN2661BC1N28 SCN2661CC1N28 SCN2661AC1A28 SCN2661BC1A28 SCN2661CC1A28 DATA BUS BUFFER HOLDING REGISTER BAUD RATE GENERATOR AND HOLDING REGISTER MODEM CONTROL PARAMETER Product specification ...
Page 3
... TEST CONDITIONS TEST CONDITIONS I = 2.2mA -400 5. 4. 0.45V O TEST CONDITIONS TEST CONDITIONS f = 1MHz C Unmeasured pins tied to ground 3 Product specification SCN2661/SCN68661 LIMITS UNIT UNIT Min Typ Max V 0.8 2 0.4 2 150 mA and t ) and at BRH BRL 20ns maximum ...
Page 4
... CPU. Transmitter The transmitter accepts parallel data from the CPU, converts serial bit stream, inserts the appropriate characters or bits (based on 4 Product specification SCN2661/SCN68661 LIMITS UNIT UNIT Min Typ Max 1000 ...
Page 5
... Apr 27 SCN2661/SCN68661 SYN/DLE Control This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the CPU. These registers are used in the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency ...
Page 6
... RxC pulse. Character assembly will start with the RxD input at this edge. XSYNC may be lowered on the next rising edge of RxD. This external synchronization will cause the SYN DETECT status bit to be set until the status register is read. Refer to XSYNC timing diagram. 6 Product specification SCN2661/SCN68661 DIVISOR — 6336 — 4224 — ...
Page 7
... General purpose output which is the complement of command register bit CR1. Normally used to indicate data terminal ready. General purpose output which is the complement of command register bit CR5. Normally used to indicate request to send. See Command Register (CR5) for details. 7 Product specification SCN2661/SCN68661 ...
Page 8
... Reading or loading the mode registers is done in a similar manner. The first write (or read) operation addresses mode register 1994 Apr 27 SCN2661/SCN68661 1, and a subsequent operation addresses mode register 2. If more than the required number of accesses are made, the internal sequencer recycles to point at the first register. The pointers are ...
Page 9
... SYN2 can be written, and SYN2 before DLE can be written. N DOUBLE SYNC TRANSPARENT MODE? LOAD SYN 2 REGISTER N N TRANSPARENT MODE? Y LOAD DLE REGISTER LOAD COMMAND REGISTER OPERATE RECONFIGURE? Y DISABLE RCVR AND XMTR Figure 1. 68661 Initialization Flowchart 9 Product specification SCN2661/SCN68661 FUNCTION SD00079 ...
Page 10
... Force (FE,OE,PE/ break DLE detect.) Not applicable Sync Send DLE 0 = Normal 1 = Send DLE 10 Product specification SCN2661/SCN68661 MR12 MR11 MR10 Mode and Baud Rate Factor 00 = Synchronous 1X rate 01 = Asynchronous 1X rate 10 = Asynchronous 16X rate 11 = Asynchronous 64X rate MR23 – MR20 Baud Rate Pin 9 ...
Page 11
... Note that automatic stripping mode does not affect the setting of the DLE detect and SYN detect status bits (SR3 and SR5). Two diagnostic sub-modes can also be configured. In local loopback mode (CR7 – CR6 = 10), the following loops are connected internally: 11 Product specification SCN2661/SCN68661 SR1 SR0 RxRDY TxRDY 0 = Receive 0 = Transmit ...
Page 12
... CPU. If equal to zero, 1994 Apr 27 SCN2661/SCN68661 there is no new character in the holding register. This bit is cleared when the CPU reads the receive data holding register or when the receiver is disabled by CR2 ...
Page 13
... Pin 9 Improved over 2651 Sink 2.2mA Source 400 A OUTPUT = 150pF L 13 Product specification SCN2661/SCN68661 PCI Not used SR3 = 1 for DLE–DLE, DLE – SYN1 Receiver disable, or CR4 = 1 Reset via CR3 on next TxRDY None First SYN1 of pair One Reset CR0 when TxEMT goes from ...
Page 14
... Apr 27 BRCLK, TxC, RxC RxD t TxD RxC (IX) READ AND WRITE BUS NOT DATA VALID VALID Product specification SCN2661/SCN68661 CLOCK t t BRH BRL t t R/TH R/TL 1/f BRG 1/f R/T RECEIVE t t RXS RXH t CED t DH BUS FLOATING SD00052 ...
Page 15
... Apr DATA 2 DATA 3 DATA 3 DATA DATA 2 DATA 3 15 Product specification SCN2661/SCN68661 SYN 1 DATA DATA 3 DATA 4 DATA 4 SD00053 ...
Page 16
... FALSE START BIT CHECK MADE (RxD LOW) 1st DATA BIT MISSING STOP BIT DETECTED, SET FE BIT. SAMPLED 0 RxD 16 Product specification SCN2661/SCN68661 t = XSYNC SETUP TIME = 300ns XSYNC HOLD TIME = ONE RxC H RHR, ACTIVATE RxRDY. SET BKDET PIN INPUT RxSR UNTIL A MARK TO SPACE TRANSITION OCCURS ...
Page 17
... READ READ RHR READ RHR STATUS (DATA 1) (DATA DATA 2 READ RHR (DATA 1) 17 Product specification SCN2661/SCN68661 DATA 4 DATA 5 IGNORED READ RHR READ RHR (DATA 3) (DATA ...
Page 18
... DATA BUS RxD EIA TO TTL CONVERT (OPT) TxD BAUD RATE CLOCK OSCILLATOR ADDRESS BUS CONTROL BUS DATA BUS RxD TxD DSR ASYNC MODEM DTR CTS RTS DCD BAUD RATE CLOCK OSCILLATOR 18 Product specification SCN2661/SCN68661 CRT TERMINAL PHONE LINE INTERFACE TELEPHONE LINE SD00082 ...
Page 19
... SYNCHRONOUS INTERFACE TO TELEPHONE LINES SCN2661/68661 1994 Apr 27 RxD TxD SYNCHRONOUS RxC TERMINAL OR PERIPHERAL TxC DEVICE ADDRESS BUS CONTROL BUS DATA BUS RxD TxD PHONE RxC LINE INTERFACE TxC SYNC DCD MODEM CTS RTS DSR DTR 19 Product specification SCN2661/SCN68661 TELEPHONE LINE SD00083 ...