scn2681 NXP Semiconductors, scn2681 Datasheet - Page 7

• Manufacturer Part Number: scn2681
• Description: Dual Asynchronous Receiver/transmitter Duart
• Manufacturer: NXP Semiconductors

Philips Semiconductors
BLOCK DIAGRAM
BLOCK DIAGRAM
The SCN2681 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the block diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
2004 Mar 18
Dual asynchronous receiver/transmitter (DUART)
X1/CLK
RESET
INTRN
D0–D7
A0–A3
WRN
CEN
RDN
X2
4
8
OPERATION CONTROL
INTERRUPT CONTROL
R/W CONTROL
BUS BUFFER
GENERATOR
SELECTORS
BAUD RATE
COUNTER/
XTAL OSC
ADDRESS
DECODE
CLOCK
TIMING
TIMER
CTUR
CSRB
CTLR
CSRA
IMR
ACR
ISR
Figure 2. Block Diagram
7
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
SHIFT REGISTER
HOLDING REG (3)
SHIFT REGISTER
SELECT LOGIC
DETECTORS (4)
HOLDING REG
OUTPUT PORT
CHANNEL A
CHANNEL B
(AS ABOVE)
INPUT PORT
CHANGE OF
FUNCTION
TRANSMIT
TRANSMIT
RECEIVE
RECEIVE
MRA1, 2
STATE
OPCR
OPR
CRA
SRA
IPCR
ACR
7
8
SCN2681
SD00085
TxDA
RxDA
TxDB
RxDB
IP0-IP6
OP0-OP7
V
GND
Product data
CC