s71ns128nc0 Meet Spansion Inc., s71ns128nc0 Datasheet - Page 5

• Manufacturer Part Number: s71ns128nc0
• Description: Stacked Multi-chip Product Mcp Mirrorbit Flash Memory And Psram 256mb 16m X 16-bit / 128mb 8m X 16-bit / 64mb 4m X 16-bit 110 Nm Cmos 1.8 Volt-only, Multiplexed, Simultaneous Read/write, Burst Mode Flash Memory With 8 Mb 512k X 16-bit
• Manufacturer: Meet Spansion Inc.

2.
March 26, 2008 S71NS-N_00_A7
Input/Output Descriptions
Table 2.1
AMAX – A16
ADQ15 – ADQ0
OE#
WE#
V
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
SS
D a t a
Symbol
identifies the input and output package connections provided on the device.
S h e e t
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is
tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges
of CLK increment the internal address counter. Should be at V
asynchronous mode
Address Valid input. Indicates to device that the valid address is present on the
address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes
starting address to be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V
four outermost sectors. Should be at V
Accelerated input. At V
unlock bypass mode. At V
V
Chip-enable input for pSRAM.
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
IH
for all other conditions.
( A d v a n c e
S71NS-N MCP Products
HH
Table 2.1 Input/Output Descriptions
, accelerates programming; automatically places device in
IL
, disables all program and erase functions. Should be at
I n f o r m a t i o n )
IL
, disables program and erase functions in the
Description
IH
for all other conditions.
IL
or V
IH
while in
Flash
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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