k4t51163qi-hpf7 Samsung Semiconductor, Inc., k4t51163qi-hpf7 Datasheet - Page 19

• Manufacturer Part Number: k4t51163qi-hpf7
• Description: 512mb I-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

14.0 General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load
Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre
sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other sim-
ulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
2. Slew Rate Measurement Levels
a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges.
c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure 2.
K4T51163QI
signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to - 500 mV
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
for falling edges).
VDDQ
VDDQ
DUT
DUT
RDQS, RDQS
DQS, DQS
RDQS
RDQS
DQS
DQS
DQ
DQ
Figure 1 - AC Timing Reference Load
Output
Output
Figure 2 - Slew Rate Test Load
Timing
reference
point
Test point
19 of 42
25
25
Ω
Ω
V
V
TT
TT
Industrial
= V
= V
DDQ
DDQ
/2
/2
Rev. 1.0 August 2009
DDR2 SDRAM