k4t51163qi-hpf7 Samsung Semiconductor, Inc., k4t51163qi-hpf7 Datasheet - Page 26
![no-image](/images/no-image-200.jpg)
k4t51163qi-hpf7
Manufacturer Part Number
k4t51163qi-hpf7
Description
512mb I-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4T51163QI-HPF7.pdf
(42 pages)
- Current page: 26 of 42
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K4T51163QI
DQS
Note1
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
V
V
V
V
V
V
Setup Slew Rate
IL(dc)
IL(ac)
REF(dc)
DDQ
IH(ac)
IH(dc)
Falling Signal
max
max
V
V
V
V
V
V
V
min
min
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
nominal
SS
Figure 8 - Illustration of tangent line for tDS (single-ended DQS)
line
V
max
max
min
min
region
REF
=
tangent line[V
to ac
∆TF
∆TF
tDS
tangent
REF(dc)
line
26 of 42
Setup Slew Rate
Rising Signal
- Vil(ac)max]
tDH
nominal
line
=
∆TR
tangent line[Vih(ac)min - V
tDS
tangent
line
∆TR
Industrial
tDH
V
REF
region
to ac
REF(dc)
Rev. 1.0 August 2009
]
DDR2 SDRAM
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