k4t51163qi-hpf7 Samsung Semiconductor, Inc., k4t51163qi-hpf7 Datasheet - Page 4

• Manufacturer Part Number: k4t51163qi-hpf7
• Description: 512mb I-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

1.0 Ordering Information
Note : 1. Speed bin is in order of CL-tRCD-tRP
2.0 Key Features
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
K4T51163QI
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 333MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
• Average Refresh Period 7.8us at -40°C < T
• All of Lead-Free products are compliant for RoHS
32Mx16
Org.
pin
strobe is an optional feature)
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products
3. “I” of Part Number(13th digit) stand for Industrial Temp./Normal Power products
4. “P” of Part Number(13th digit) stand for Industrial Temp./Low Power products
5. “D” of Part Number(13th digit) stand for Industrial Temp./Super Low Power products
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
Speed
-PASR(Partial Array Self Refresh)
-50ohm ODT
-Support Industrial Temp.(Case Temp. -40 to 95°C)
CK
for 667Mb/sec/pin, 400MHz f
K4T51163QI-HPE7
K4T51163QI-HDE7
K4T51163QI-HIE7
DDR2-800 5-5-5
DDR2-800 5-5-5
12.5
12.5
57.5
5
CK
CASE
for 800Mb/sec/
< 95 °C
K4T51163QI-HPF7
K4T51163QI-HIF7
DDR2-800 6-6-6
4 of 42
DDR2-800 6-6-6
-
15
15
60
The 512Mb DDR2 SDRAM is organized as a 8Mbit x 16 I/Os x 4
banks device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V V
The 512Mb DDR2 device is available in 84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
6
Industrial
K4T51163QE-HDE6
DDR2-667 5-5-5
K4T51163QI-HPE6
K4T51163QI-HIE6
DDR2-667 5-5-5
15
15
60
5
DDQ
Rev. 1.0 August 2009
.
DDR2 SDRAM
Units
84 FBGA
Package
tCK
ns
ns
ns