saa4961 NXP Semiconductors, saa4961 Datasheet - Page 8

• Manufacturer Part Number: saa4961
• Description: Saa4961 Integrated Multistandard Comb Filter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Main tasks of the control and clock processing are:
The signal processing is based on a 3
(CL3), that is generated by the clock processing from the
f
frequency divided by the line frequency results not in an
integer value a clock phase correction of 180 is necessary
every second line for PAL standards or every line for
NTSC standard. The clock phase correction is controlled
by the input signals horizontal sync. Additionally the delay
line start is synchronized once a field to the input signals
horizontal sync. The 25 Hz PAL offset is corrected in this
way.
The PLL provides a master clock MCK of 6
locked to the subcarrier frequency at FSC (pin 1).
The system clock CL3 (3
divide-by-two circuit. The 180 phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle.
The generated clock is a pseudo-line-locked clock that is
referenced to f
necessary signals H
and the field (V) sync periods.
The current mode of operation (BYPASS or COMB) is
external readable via COMBENA (pin 25).
The input signals of the control and clock processing
(CLOCK CONTROL) are:
The output signals are:
1997 Feb 03
sc
Clock generation of system clock CL3
Delay line start control
Mode control.
H
V
FSC: subcarrier frequency (f
FSCSW: reference frequency selection
BYP: BYPASS control signal
SSYN: vertical synchronous mode selection for BYP
and polarity selection of BYP.
CL3: system clock (3
HSEL: line start signals for the delay lines
STOPS: forces the comb filter via the switches S2A,
S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or
asynchronous with V
COMBENA: HIGH during COMB-mode; otherwise
LOW.
Integrated multistandard comb filter
signal at FSC (pin 1) via a PLL. Because the subcarrier
DET
DET
: analog vertical pulse from sync separator
: analog horizontal pulse from sync separator
sc
. The sync separator generates the
DET
INT
and V
f
; depending on SSYN)
sc
f
sc
)
) is obtained from MCK by a
DET
sc
or 2
indicating the line (H)
f
sc
f
sc
)
system clock
f
sc
, which is
8
Table 11 Function of STOPS signal
H
A built-in sync separator circuit generates the H
V
is still operating properly at input signals with a 12 dB
attenuated sync in a normal 700 mV black-to-white video
signal (see Fig.4).
C
The black level clamping of the video input signal is
performed by the sync separator stage. The clamping level
is nearly adequate to the voltage at REFDL (pin 24).
S
The switch is included to bypass the low-pass input filter.
For the CVBS input of the delay line block two signals can
be selected via the slow signal switch S1.
Table 12 Function of signal switch S1
S
For the CVBSO output two signals can be selected via the
signal switch S2A.
Table 13 CVBSO output signal
S
Two switches are included to bypass the comb filter signal
processing. The input video signal C
is internally biased.
LOW
HIGH
LOW
HIGH
Floating
LOW
HIGH
LPFION-STATE
STOPS-STATE
DET
IGNAL SWITCH
IGNAL SWITCH
STOPS-STATE
IGNAL SWITCH
ORIZONTAL AND VERTICAL SYNC SEPARATOR
LAMP
signals from the Y
S1
S2A
S2B
COMB
BYPASS
non-pre-filtered input signal
Y
pre-filtered input signal Y
pre-filtered input signal Y
delayed input CVBSDL
non-delayed input
Y
AND
ext
ext
/CVBS
CVBSO OUTPUT
/CVBS
ext
S2C
/CVBS input signal. This circuit
DELAY LINE INPUT
SIGNAL
SELECTED MODE
Preliminary specification
ext
for the switch S2C
SAA4961
ext
ext
COMB
BYPASS
/CVBS
/CVBS
DET
MODE
and