saa4700t NXP Semiconductors, saa4700t Datasheet - Page 3

• Manufacturer Part Number: saa4700t
• Description: Saa4700t Vps Dataline Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Dataline 16
The information in dataline 16 consists of fifteen 8-bit
words; the total information content is shown in Table 1;
and the organization of transmitted bytes is shown in
Table 2.
Out of the fifteen possible 8-bit words the SAA4700T
extracts words 5 and 11 to 14. The contents of these words
can be read via the built-in I
fully transparent, thus each bit is transferred without
modification with only the sequence of words being
changed. Words 11 to 14 are transmitted first followed by
word 5.
By evaluating the sliced sync signal the circuit can identify
the beginning of dataline 16 in the first field. The dataline
decoder stage releases the start code detector. When a
March 1991
handbook, full pagewidth
VPS dataline processor
470 pF
CVBS
to V P
4.7
k
8.2 k
4.7 nF
22
nF
75 k
(2%)
4.7 nF
1 nF
15
19
2
1
PHASE DETECTOR
SEPARATOR
SAA4700T
5 MHz VCO AND
REGENERATOR
SLICER
2
SYNC
DATA
PLL WITH
C-bus interface. The circuit is
CLOCK
5
0.1
F
line 16
CSO
data
VCS
Fig.1 Block diagram and test circuit.
6
clock pulse
LINE 16 DECODER
FIELD SELECTOR
16
CONTROLLER
INPUT
(test line 16)
12
3
correct start code is detected (for timing of start code
detection see Fig.3) words 5 and 11 to 14 are decoded,
checked for biphase errors and stored in a register bank. If
no biphase error has occurred, the contents of the register
bank are transferred to a second register bank by the data
valid control signal. If the system has been addressed, this
transfer will be delayed until the next start or stop condition
of the I
The last bit of correct information on the dataline remains
available until it is read via the I
information has been read it is considered to be no longer
valid and the internal new data flag is reset. Subsequently,
if the circuit is addressed, the only VPS data that will be
sent back is “FFF to F”. The same conditions apply after
power-up when no data can be read out. New data is
available after reception of another error-free dataline 16.
TIME BASE
2
C-bus has been received.
data
CONTROLLER
4
6
OUTPUT
POWER-ON RESET
DAV
3
REFERENCE
13
VOLTAGES
MULTIPLEXER
4
DATA LATCH
40 BIT DATA
0.1 F
REGISTER
5
40 BIT
17
CONTROL
2
I
18
C-bus. Once the stored
2
Preliminary specification
C-BUS
8
external
8
reset
AD = LOW
SAA4700T
V P
11
5 V
14
20
10
7
9
MGH128
n.c.
n.c.
n.c.
SCL
SDA