mt18hts25672pky Micron Semiconductor Products, mt18hts25672pky Datasheet - Page 11

• Manufacturer Part Number: mt18hts25672pky
• Description: Ddr2 Sdram Mini-rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 9: I
Values are shown for the MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie
(256 Meg x 8) component data sheet
PDF: 09005aef82218d23
hts18c256_512x72pky.pdf - Rev. C 3/10 EN
Parameter/Condition
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
tween valid commands; Address bus inputs are stable during deselects; Data bus
inputs are switching
DD
RCD (I
CK (I
RP (I
OUT
RP =
OUT
RC =
DD
),
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
DD
Specifications
t
t
t
RAS =
DD
RP (I
RC (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DD
DD
DD
t
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
),
Specifications and Conditions – 2GB
t
RRD =
t
RP (I
t
CK =
DD
t
RRD (I
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
DD
t
CK (I
), AL = 0;
), AL =
),
),
t
t
RC =
RCD =
DD
t
CK =
); REFRESH command at every
t
RCD (I
t
DD4W
RC (I
t
t
CK =
t
RCD (I
CK (I
DD
DD
t
),
DD
CK (I
) - 1 x
DD
t
),
RAS =
); CKE is HIGH, S# is HIGH be-
t
CK =
t
t
RAS =
CK =
DD
t
CK =
t
CK (I
),
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
t
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
CK (I
t
OUT
t
CK =
t
RAS MAX (I
DD
t
CK (I
CK =
11
);
DD
= 0mA; BL = 4, CL
DD
t
t
),
CK =
t
RAS MAX (I
DD
CK (I
),
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK (I
RAS =
); CKE is HIGH,
t
DD
RC =
t
RFC (I
t
DD
),
CK (I
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
t
),
); CKE is
RC
RAS
DD
DD
t
RP =
DD
),
)
),
Symbol
I
I
I
I
I
I
I
CDD4W
I
I
CDD2Q
CDD2N
CDD3N
I
I
I
CDD2P
CDD3P
CDD4R
CDD0
CDD1
CDD5
CDD6
CDD7
© 2006 Micron Technology, Inc. All rights reserved.
1098
1548
1548
2223
3123
-80E
918
126
513
558
333
153
648
126
I
DD
Specifications
1008
1323
1323
2043
2628
-667
873
126
423
468
333
153
603
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA