mt18ld472fg-5 Micron Semiconductor Products, mt18ld472fg-5 Datasheet - Page 13

• Manufacturer Part Number: mt18ld472fg-5
• Description: 2, 4 Meg X 72 Buffered Dram Dimms
• Manufacturer: Micron Semiconductor Products

OBSOLETE
NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10.If CAS# = V
11.If CAS# = V
12.Measured with a load equivalent to two TTL gates
13.Requires that
14.Requires that
15.If CAS# is LOW at the falling edge of RAS#, Q will
16.The
17.The
18.Either
2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
values are obtained with minimum cycle time and
the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured.
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
2.5ns for EDO.
measuring timing of input signals. Transition times
are measured between V
and V
specification, all input signals must transit between
V
tonic manner.
the last valid READ cycle.
and 100pF and V
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
must always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
or without the
t
cycle.
REF refresh requirement is exceeded.
RCD was greater than the specified
RAD was greater than the specified
CAC must always be met.
CC
IH
IH
t
t
is dependent on output loading. Specified
(MIN) and V
and V
CAC (
AA (
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
IH
t
RCH or
).
t
RAC and
IL
t
RAC [MIN] no longer applied). With or
(or between V
IH
IL
t
RCD (MAX) limit,
, data output may contain data from
, data output is High-Z.
t
t
AA and
AA and
t
t
RRH must be satisfied for a READ
RAD (MAX) limit,
IL
OL
(MAX) are reference levels for
t
CAC no longer applied). With
= 0.8V and V
t
t
CAC are not violated.
RAC are not violated.
IH
IL
t
t
and V
CP.
T = 5ns for FPM and
SS
and V
DD
.
= +3.3V; f = 1 MHz.
t
IL
AA and
OH
IH
(or between V
t
) in a mono-
AA,
= 2V.
t
t
RCD (MAX)
RAD (MAX)
t
RAC and
t
CAC
t
t
RCD
RAD
IL
13
19.
20.A HIDDEN REFRESH may also be performed after
21.A +2ns timing skew from the DRAM to the
22.A -2ns timing skew from the DRAM to the module
23.A +5ns timing skew from the DRAM to the
24.A -2ns (MIN) and a -5ns (MAX) timing skew from
25.A +2ns (MIN) and a +5ns (MAX) timing skew from
26.LATE WRITE and READ-MODIFY-WRITE cycles
27.These parameters are referenced to CAS# leading
28.
29.Column address changed once each cycle.
30.The 3ns minimum parameter guaranteed by
t
achieves the open circuit condition and is not
referenced to V
a WRITE cycle. In this case, WE# = LOW and OE#
= HIGH.
module resulted from the addition of line drivers.
resulted from the addition of line drivers.
module resulted from the addition of line drivers.
the DRAM to the module resulted from the
addition of line drivers.
the DRAM to the module resulted from the
addition of line drivers.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
to OE# going back LOW, the DQs will remain
open.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
t
operating parameters.
WRITE cycles.
READ-MODIFY-WRITE cycles. If
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit through-
out the entire cycle. If
t
t
MODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WRITE cycle.
design.
OFF (MAX) defines the time at which the output
WCS,
RWD
CWD
CWD and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RWD,
t
t
BUFFERED DRAM DIMMs
CWD (MIN), the cycle is a READ-
RWD (MIN),
t
t
OEH is met. If CAS# goes HIGH prior
AWD are not applicable in a LATE
t
AWD and
t
OH
RWD,
t
OD and
or V
t
OL
t
AWD and
t
WCS applies to EARLY
t
WCS <
AWD
.
t
t
CWD are not restrictive
OEH met (OE# HIGH
2, 4 MEG x 72
t
t
WCS (MIN) and
t
WCS,
AWD (MIN) and
t
t
WCS
CWD apply to
©1999, Micron Technology, Inc.
t
RWD,
t
WCS