mt18ld472fg-5 Micron Semiconductor Products, mt18ld472fg-5 Datasheet - Page 5

• Manufacturer Part Number: mt18ld472fg-5
• Description: 2, 4 Meg X 72 Buffered Dram Dimms
• Manufacturer: Micron Semiconductor Products

OBSOLETE
PIN DESCRIPTIONS
2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
29, 41-42, 47, 61-64, 111,
91-95, 97-101, 103-106,
52-53, 55-58, 60, 65-67,
113, 115, 125, 128, 131,
6, 18, 26, 40, 49, 59, 73,
68, 78, 85, 96, 107, 116,
2-5, 7-11, 13-17, 19-22,
144, 149-151, 153-156,
84, 90, 102, 110, 124,
69-72, 74-77, 86-89,
1, 12, 23, 32, 43, 54,
33-38, 117-122, 126
136-137, 139-142,
133, 143, 157, 168
127, 138, 152, 162
PIN NUMBERS
79-82, 163-166
158-161
145-148
83, 167
30, 45
28, 46
27, 48
31, 44
132
RAS0#, RAS2#
CAS0#, CAS4#
WE0#, WE2#
OE0#, OE2#
A0-A11, B0
DQ0-DQ71
SYMBOL
PD1-PD8
ID0, ID1
PDE#
RFU
V
V
DD
SS
Buffered
Buffered
Buffered
Buffered
Buffered
Output
Output
Supply
Supply
Input/
Output
TYPE
Input
Input
Input
Input
Input
Input
–
5
Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x72 bank
or two x36 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ35. WE2# controls
DQ36-DQ71. If WE# is LOW prior to CAS# going LOW,
the access is an EARLY WRITE cycle. If WE# is HIGH
while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
Output Enable: OE# is the input/output control for the
DQ pins. OE0# controls DQ0-DQ35. OE2# controls
DQ36-DQ71. These signals may be driven, allowing
LATE WRITE cycles.
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#. A0 is common to the
DRAMs used for DQ0-DQ35 while B0 is common to the
DRAMs used for DQ36-DQ71
Data I/O: For WRITE cycles, DQ0-DQ71 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ71 act as outputs for the addressed DRAM
location.
Presence-Detect: These pins are read by the host system
and tell the system the DIMM’s personality. They will be
either no connect (1), or they will be driven to V
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ± 0.3V.
Ground.
ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (V
Presence-Detect Enable: PDE# is the READ control for
the buffered presence-detect pins.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
BUFFERED DRAM DIMMs
).
DESCRIPTION
2, 4 MEG x 72
©1999, Micron Technology, Inc.
OL
(0).