m470l6423ck0 Samsung Semiconductor, Inc., m470l6423ck0 Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
m470l6423ck0
Manufacturer Part Number
m470l6423ck0
Description
512mb Ddr Sdram Module 64mx64 Based On Ddp 64mx 8 Ddr Sdram 200pin Sodimm 64bit Non-ecc/parity
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M470L6423CK0.pdf
(14 pages)
M470L6423CK0
6. Input Setup/Hold Slew Rate Derating
7. I/O Setup/Hold Slew Rate Derating
8. I/O Setup/Hold Plateau Derating
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
10. This parameter is fir system simulation purpose. It is guranteed by design.
This derating table is used to increase t
This derating table is used to increase t
based on the lesser of AC-AC slew rate and DC-DC slew rate.
based on the lesser of AC-AC slew rate and DC-DC slew rate.
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF
This derating table is used to increase t
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
up to 2ns.
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
Input Setup/Hold Slew Rate
I/O Setup/Hold Slew Rate
Delta Rise/Fall Rate
I/O Input Level
(V/ns)
(V/ns)
(ns/V)
(mV)
0.5
0.4
0.3
0.5
0.4
0.3
0.25
0.5
280
0
DS
IS
DS
/t
/t
/t
+100
+150
+100
IH
DH
(ps)
+50
(ps)
+75
(ps)
+50
(ps)
+50
DH
tDS
tDS
tDS
tIS
0
0
0
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
+100
+150
+100
(ps)
+50
(ps)
+75
(ps)
+50
(ps)
+50
tDH
tDH
tDH
tIH
0
0
0
200pin DDR SDRAM SODIMM
Rev. 0.0 Aug. 2001
310mV for a duration of