m470l6423ck0 Samsung Semiconductor, Inc., m470l6423ck0 Datasheet - Page 13

• Manufacturer Part Number: m470l6423ck0
• Description: 512mb Ddr Sdram Module 64mx64 Based On Ddp 64mx 8 Ddr Sdram 200pin Sodimm 64bit Non-ecc/parity
• Manufacturer: Samsung Semiconductor, Inc.

Command Truth Table
M470L6423CK0
Register
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Active Power Down
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A
2. EMRS/ MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA
5. If A
6. During burst write with auto precharge, new read/write command can not be issued.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
7. Burst stop command is valid at every burst length.
A new command can be issued 2 clock cycles after EMRS or MRS.
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If both BA
If both BA
If both BA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
The automatical precharge without row precharge command is meant by "Auto".
0
10
~ BA
/AP is "High" at row precharge, BA
COMMAND
1
0
0
0
0
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
: Bank select addresses.
and BA
is "High" and BA
is "Low" and BA
and BA
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
Entry
Entry
Entry
1
1
Exit
Exit
Exit
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
0
~ A
12
& BA
CKEn-1
0
and BA
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
~ BA
1
CKEn
1
are ignored and all banks are selected.
: Program keys. (@EMRS/MRS)
X
X
H
H
X
X
X
X
X
H
H
X
(V=Valid, X=Don t Care, H=Logic High, L=Logic Low)
L
L
L
RP
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
L
after the end of burst.
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
200pin DDR SDRAM SODIMM
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
L
WE
H
H
H
H
H
H
L
L
X
L
L
L
X
V
X
X
X
V
X
BA
V
V
V
V
X
0,1
Rev. 0.0 Aug. 2001
A
OP CODE
OP CODE
10
H
H
H
Row Address
L
L
L
/AP
X
X
X
X
X
X
X
A
A
Address
Address
Column
Column
(A
(A
12
9
0
0
X
~ A
~A
~A
, A
9
9
11
)
)
0
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9