m470l6423ck0 Samsung Semiconductor, Inc., m470l6423ck0 Datasheet - Page 3

• Manufacturer Part Number: m470l6423ck0
• Description: 512mb Ddr Sdram Module 64mx64 Based On Ddp 64mx 8 Ddr Sdram 200pin Sodimm 64bit Non-ecc/parity
• Manufacturer: Samsung Semiconductor, Inc.

M470L6423CK0 200pin DDR SDRAM SODIMM
64Mx64 200pin DDR SDRAM SODIMM based on DDP 64Mx8
M470L6423CK0
GENERAL DESCRIPTION
Rate SDRAM high density memory modules based on 4th gen
of 256Mb DDR SDRAM respectively.
The Samsung M470L6423CK0 consists of eight CMOS DDP
64M x 8 bit with 4banks Double Data Rate SDRAMs in 54pin
TSOP-II(400mil) packages mounted on a 200pin glass-epoxy
substrate. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM.
The M470L6423CK0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
The Samsung M470L6423CK0 is 64M bit x 64 Double Data
Synchronous design allows precise cycle control with the use
PIN CONFIGURATIONS (Front side/back side)
Pin
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
1
3
5
7
9
Key
VREF
DQS0
DQS1
DQ10
DQ11
DQ16
DQ17
DQS2
DQ18
DQ19
DQ24
DQ25
DQS3
DQ26
Front
/CK0
VDD
VDD
VDD
VDD
VDD
VSS
DQ0
DQ1
DQ2
VSS
DQ3
DQ8
DQ9
VSS
CK0
VSS
VSS
VSS
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DU(A13)
A10/AP
DQS8
DQS4
Front
DQ27
CKE1
DQ32
DQ33
VDD
VDD
/CK2
VDD
VDD
VDD
CB0
CB1
VSS
CB2
CB3
VSS
CK2
VSS
VSS
A12
BA0
/WE
DU
/S0
DU
A9
A7
A5
A3
A1
Pin
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VDDSPD
VDDID
DQ34
DQ35
DQ40
DQ41
DQS5
DQ42
DQ43
DQ48
DQ49
DQS6
DQ50
DQ51
DQ56
DQ57
DQS7
DQ58
DQ59
Front
VDD
VDD
VDD
VDD
VDD
VDD
SDA
VSS
VSS
VSS
VSS
VSS
VSS
SCL
Pin
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
2
4
6
8
Key
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
Back
VDD
DM0
VDD
DM1
VDD
VDD
VDD
DM2
VDD
DM3
VSS
DQ4
DQ5
DQ6
VSS
DQ7
VSS
VSS
VSS
VSS
VSS
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
Pin
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
DU/(RESET)
DU(BA2)
DQ31
CKE0
DQ36
DQ37
Back
/RAS
/CAS
VDD
DM8
VDD
VDD
VDD
VDD
VDD
DM4
CB4
CB5
VSS
CB6
CB7
VSS
VSS
VSS
BA1
VSS
A11
/S1
DU
A8
A6
A4
A2
A0
• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
•
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 (mil), double sided component
FEATURE
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Pin
M470L6423CK0-C(L)A2 133MHz(7.5ns@CL=2)
M470L6423CK0-C(L)B0 133MHz(7.5ns@CL=2.5)
M470L6423CK0-C(L)A0 100MHz(10ns@CL=2)
Double-data-rate architecture; two data transfers per clock cycle
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
Back
VDD
DM5
VDD
/CK1
VDD
DM6
VDD
DM7
VDD
VSS
VSS
CK1
VSS
VSS
VSS
SA0
SA1
SA2
DU
Part No.
200pin DDR SDRAM SODIMM
PIN DESCRIPTION
*
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0~ CK2,
CK0~ CK2
CKE0 ~ CKE1
CS0 ~ CS1
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
These pins are not used in this module.
Pin Name
Max Freq.
Rev. 0.0 Aug. 2001
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
Function
Interface
SSTL_2