hys64d320x0edl-5-d Qimonda, hys64d320x0edl-5-d Datasheet - Page 20

• Manufacturer Part Number: hys64d320x0edl-5-d
• Description: 200-pin Small Outline Dual -in-line Memory Modules
• Manufacturer: Qimonda

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) For each of the terms, if not already an integer, round to the next highest integer.
7)
Rev. 0.60, 2008-05
05282008-IARQ-5WHU
Parameter
Address and control input setup
time
Data-out low-impedance time
from CK/CK
Mode register set command
cycle time
DQ/DQS output hold time
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh
Interval
Auto-refresh to Active/Auto-
refresh command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
HZ
and
T
t
A
LZ
≤ 70 °C
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
; V
DDQ
V
REF
= 2.5 V ± 0.2 V,
. CK/CK slew rate are ≥ 1.0 V/ns.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IS
LZ
MRD
QH
QHS
RAP
RAS
RC
RCD
REFI
RFC
RP
RPRE
RPST
RRD
WPRE
WPRES
WPST
WR
WTR
XSNR
XSRD
V
REF
V
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
–5
DDR400B
Min.
0.6
0.7
–0.7
2
t
—
t
40
55
15
—
70
15
0.9
0.40
10
0.25
0
0.40
15
2
75
200
HP
RCD
–
t
QHS
20
Max.
—
—
+0.7
—
—
+0.50
—
70E+3
—
—
7.8
—
—
1.1
0.60
—
—
—
0.60
—
—
—
—
V
DDQ
= 2.6 V ± 0.1 V,
–6
DDR333
Min.
0.75
0.8
–0.7
2
t
—
t
42
60
18
—
72
18
0.9
0.40
12
0.25
0
0.40
15
1
75
200
HP
RCD
t
CK
–
is equal to the actual system clock cycle time.
t
QHS
Small Outline DDR SDRAM Modules
V
HYS64D[32/64]0x0EDL–[5/6]–D
DD
= +2.6 V ± 0.1 V (DDR400)
Max.
—
—
+0.7
—
—
+0.55
—
70E+3
—
—
7.8
—
—
1.1
0.60
—
—
—
0.60
—
—
—
—
Advance Internet Data Sheet
Unit
ns
ns
ns
t
ns
ns
ns
ns
ns
ns
μs
ns
ns
t
t
ns
t
ns
t
ns
t
ns
t
CK
CK
CK
CK
CK
CK
CK
Note/ Test
Condition
Fast slew rate
3)4)5)6)9)
Slow slew rate
3)4)5)6)10)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
V
TT
.
2)3)4)5)
1)