mt9vddf6472y-335 Micron Semiconductor Products, mt9vddf6472y-335 Datasheet - Page 22

• Manufacturer Part Number: mt9vddf6472y-335
• Description: 256mb, 512mb X72, Ecc, Sr 184-pin Ddr Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
33. Normal Output Drive Curves:
160
140
120
100
Figure 10: Pull-Down Characteristics
80
60
40
20
0
0.0
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+400mV (2.9V max), whichever is less. Any nega-
tive glitch must be less than 1/3 of the clock cycle
and not exceed -300mV (2.2V min), whichever is
more positive. However, the DC average cannot be
below 2.3V minimum.
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current from
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
from minimum to maximum process, tempera-
ture and voltage will lie within the outer bound-
ing lines of the V-I curve of Figure 10, Pull-Down
Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 10, Pull-Down Characteristics.
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 11, Pull-Up Char-
acteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
11, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
RAS(MIN) can be satis-
1.5
2.0
Minimum
2.5
22
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -335, -262, -26A and -265, I
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
Figure 11: Pull-Up Characteristics
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
width 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. V
= -1.5V for a pulse width 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
equal to or less than V
may be 1.35V maximum during power up, even if
V
series resistance is used between the V
and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
be 35mA at 100 MHz.
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and tRPRE begin point are not
256MB, 512MB (x72, ECC, SR)
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
DD
RPST), or begins driving (
DD
184-PIN DDR SDRAM RDIMM
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
overshoot: V
/V
and V
t
DQSCK (MIN) +
DDQ
DD
0.5
DDQ
are 0V, provided a minimum of 42 of
level and the referenced test load. In
must track each other.
IH
(MAX) = V
1.0
V
DD
t
Q - V
DD
RPRE (MAX) condition.
DDQ
©2004 Micron Technology, Inc. All rights reserved.
OUT
+ 0.3V. Alternatively, V
IL
t
t
, V
(V)
LZ (MIN) will prevail
RPRE).
DDQ
1.5
undershoot: V
TT
DD
t
, and V
DQSCK (MAX) +
+ 1.5V for a pulse
3N is specified to
2.0
REF
TT
must be
IL
supply
(MIN)
2.5
TT