mt9vddf6472y-335 Micron Semiconductor Products, mt9vddf6472y-335 Datasheet - Page 26

• Manufacturer Part Number: mt9vddf6472y-335
• Description: 256mb, 512mb X72, Ecc, Sr 184-pin Ddr Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
NOTE:
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
PARAMETER
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
1. Timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM Registered
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its ref-
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
7. The Output Slew Rate is determined from the IBIS model:
DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed informa-
tion for this PLL is available in JEDEC Standard JESD82.
meet the other timing parameters. (Used for low-speed system debug.)
erence signal after power up.
other.
SYMBOL
t
t
t
JIT
t
STAB
JIT
t
t
t
JIT
f
t
SK
t
LS
DC
CK
LS
HPER
PER
CC
O
O
I
MIN
-100
-75
-50
-75
1.0
1.0
60
40
-
-
V
26
0°C
DD
NOMINAL
CDCV857
= +2.5V ±0.2V
GND
T
V
0
-
-
-
-
-
-
-
-
-
DD
A
256MB, 512MB (x72, ECC, SR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
+70°C
V
V
MAX
CK
CK
170
100
100
100
R=60
R=60
60
75
50
75
4
2
V
DD
/2
©2004 Micron Technology, Inc. All rights reserved.
UNITS
MHz
V/ns
V/ns
ms
%
ps
ps
ps
ps
ps
NOTES
2, 3
4
5
6
6
7