mt9vddf6472phy-335 Micron Semiconductor Products, mt9vddf6472phy-335 Datasheet - Page 10

• Manufacturer Part Number: mt9vddf6472phy-335
• Description: 256mb, 512mb X72, Ecc, Pll, Sr 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

General Description
PLL Operation
Serial Presence-Detect Operation
Table 5:
PDF: 09005aef81eef7d4/Source: 09005aef81eef0df
DDF9C32_64x72PH_2.fm - Rev. A 1/06 EN
CAS Latency (CL) Table
The Micron MT9VDDF3272PH and MT9VDDF6472PH are high-speed CMOS, dynamic
random-access, 256MB and 512MB memory modules organized in x72 (ECC) configura-
tion. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM device during READs and by the memory controller during WRITEs. DQS is
edge-aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK. A phase-lock loop (PLL) device on the
module is used to redrive the differential clock signals to the DDR SDRAM devices to
minimize system clock loading.
A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK
and CK# to the DDR SDRAM devices to minimize system clock loading.
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-
age are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
Speed
-26A
-335
-262
-265
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
10
Allowable Operating Clock Frequency (MHz)
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
CL = 2
N/A
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2005 Micron Technology, Inc. All rights reserved.
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
CL = 2.5
2
C