saa5290ps NXP Semiconductors, saa5290ps Datasheet - Page 47

• Manufacturer Part Number: saa5290ps
• Description: Economy Teletext And Tv Microcontrollers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9.20
The vertical display timing also resynchronizes to every
sync pulse received. This means that the device can
produce a stable display on both 625 and 525-line
screens. Display starts on the 41st line of each field and
continues for 250 lines, or until the end of the field.
Normally, television displays are interlaced, i.e. only every
other TV line is displayed on each field. It is normal to
de-interlace teletext displays to prevent the displayed
characters flickering up and down. In many TV designs this
is achieved by modulating the vertical deflection current in
such a way that odd fields are shifted up and even fields
are shifted down on the screen so that lines 1 and 314,
2 and 315 etc. are overlaid. The FRAME output is
provided to facilitate this.
The odd/even field decision is made on the timing between
the active edge of Hsync and the active edge of the Vsync
pulses. The active edge is programmed using the TXT1
register H polarity and V polarity bits.
The timing windows are designed to prevent the FRAME
output oscillating from odd to even, these are detailed
below:
The algorithm used to derive Frame is such that a
consistent output will be obtained no matter where the
Vsync signal is relative to the Hsync signal, even if Vsync
occurs at the start and mid points of a line.
1998 Dec 14
If H to V is 0 to 16 s then output is even (FRAME = 0)
If H to V is 16 to 32 s then output is based on previous
field (i.e. previous value of FRAME)
If H to V is 32 to 48 s then output is odd (FRAME = 1)
If H to V is 48 to 64 s then output is based on previous
field (i.e. previous value of FRAME).
Economy teletext and TV microcontrollers
Vertical timing
47
Setting the TXT0.DISABLE FRAME bit forces the FRAME
output to a logic 0. Setting the TXT0.AUTO FRAME bit
causes the FRAME output to be active when just text is
being displayed but to be forced to a logic 0 when any
video is being displayed. This allows the de-interlacing
function to take place with virtually no software
intervention.
Some TV architectures do not use the FRAME output but
accomplish the de-interlacing function in the vertical
deflection IC, under software control, by delaying the start
of the scan for one field by half a line, so that lines in this
field are moved up by one TV line. In such TVs, Vsync may
occur in the first half of the line at the start of an odd field
and in the second half of the line at the start of an even
field. In order to obtain correct de-interlacing in these
circumstances, the TXT1.FIELD POLARITY must be set
to reverse the assumptions made by the vertical timing
circuits on the timing of Vsync in each field. The start of the
display may be delayed by a line. The ‘Field Polarity’ bit
does not affect the FRAME output.
handbook, halfpage
TUNER/IF
CVBS
Fig.14 Timing configuration.
DECODING
CIRCUITS
VIDEO
SYNC
SAA5x9x
HSYNC, VSYNC
RGB
SAA5x9x family
Preliminary specification
RGB, VDS
FRAME
DISPLAY
CRT
MGK464