w83c553f Winbond Electronics Corp America, w83c553f Datasheet

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w83c553f

Manufacturer Part Number
w83c553f
Description
System I/o Controller With Pci Arbiter
Manufacturer
Winbond Electronics Corp America
Datasheet

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DATA BOOK
W83C553F
SYSTEM I/O
CONTROLLER
WITH PCI
ARBITER
A
Company
Publication number: 2565; Version A.7.0d.1

Related parts for w83c553f

w83c553f Summary of contents

Page 1

... DATA BOOK W83C553F SYSTEM I/O CONTROLLER WITH PCI ARBITER A Company Publication number: 2565; Version A.7.0d.1 ...

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...

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Copyright Notice Copyright 1995, 1996, 1997 WINBOND SYSTEMS LABORATORY. All rights reserved. Issued: September 27, 1995 Publication no: 2565; Ver. A.6 Issued: October 1, 1996 Publication no: 2565; Ver. A.6.2 Issued: March 1, 1997 Publication no: 2565; Ver. A.7.0b Issued: ...

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... W83C553F PREFACE This document describes the function and use of the Winbond Systems Laboratory W83C553F System I/O (SIO) Controller with PCI arbiter. It provides all of the information necessary for design engineers to incorporate the device into notebook and desktop computer systems. Organization of the Manual The information in this document is organized into the following seven chapters: ...

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... W83C553F WINBOND SYSTEMS LABORATORY Table of Contents 2 ...

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... W83C553F TABLE OF CONTENTS Preface............................................................................................................................................... 1 1.0 General Information ................................................................................................... 5 1.1 Features .................................................................................................................... 5 1.2 General Description ................................................................................................... 7 1.3 Stylistic Conventions Used in this Manual .................................................................. 9 2.0 Pin Descriptions................................................................................................................... 10 2.1 Pin Assignments ........................................................................................................ 10 2.2 Pin Description........................................................................................................... 13 3.0 System Architecture............................................................................................................. 28 3.1 Overview ................................................................................................................... 28 3.2 Active State ............................................................................................................... 29 3.3 Bus Structures ........................................................................................................... 30 3.4 PCI-to-ISA Bridge ...................................................................................................... 31 3.5 PCI Bus Cycles.......................................................................................................... 31 3.6 PCI I/O Read Cycle ................................................................................................... 34 3.7 PCI I/O Write Cycle ................................................................................................... 35 3.8 PCI Configuration Read Cycle ................................................................................... 36 3 ...

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... W83C553F 4.3.2 Function 1 Control Registers ...................................................................... 123 4.4 Bus Master IDE (Function 1) I/O Registers................................................................. 129 4.4.1 Primary/Secondary Command Registers.................................................... 130 4.4.2 Primary/Secondary Status Registers .......................................................... 131 4.4.3 Primary/Secondary PRD Table.................................................................. 132 5.0 Electrical Specifications ...................................................................................................... 133 6.0 Timing Diagrams .................................................................................................................. 135 6.1 PCI Timing Diagrams................................................................................................. 136 6.2 IDE/ATA Data Transfers ............................................................................................ 142 6.3 ISA Bus Timing.......................................................................................................... 150 7 ...

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... W83C553F 1.0 GENERAL INFORMATION 1.1 Features High Integration PCI-ISA solution • Optimized for lowest system cost • Complies with PCI Revision 2.0 specification • Universal PCI device supporting x86 and PowerPC (non-x86) modes of operation Nand tree on most signal pins to facilitate board level testing in PCB manufacturing environment Integrated PCI Bus Master IDE controller • ...

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... W83C553F Power Management Break Event support for Green PC applications Built-in Integrated Peripheral Controller (IPC) with standard PC-AT peripherals • Two 82C37A DMA controllers (types A, B, and F) - 32-bit addressing allows use of alternate CPUs, such as PowerPC - supports multiple 8-bit and 16-bit scatter/gather DMA channels • ...

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... General Description The W83C553F Enhanced System I/O (SIO) Controller with PCI Arbiter is a highly integrated device intended for use in any Peripheral Component Interconnect (PCI) system, supporting x86 or PowerPC (non-x86) type microprocessors. It supports all PCI 2.1 compliant CPU bridge implementations and directly interfaces with PCI and ISA industry standard buses, including two direct drive IDE channels supporting up to four peripherals ...

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... W83C553F Figure 1-1. W83C553F Enhanced System I/O Controller Block Diagram WINBOND SYSTEMS LABORATORY General Information 8 ...

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... W83C553F 1.3 Stylistic Conventions Used in this Manual The following stylistic conventions have been used throughout this manual: • Signal names: Signals that are active at a low voltage level are indicated by a pound sign (#) after the signal name. Signal names not followed by the # are active at the high voltage level. ...

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... W83C553F 2.0 PIN DESCRIPTIONS This chapter shows the pin diagrams, pins listed by pin number, device logic symbols, and describes each pin signal for the W83C553F. 2.1 Pin Assignments Figure 2-1. Pin Assignments for the W83C553F WINBOND SYSTEMS LABORATORY Pin Descriptions 10 ...

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... W83C553F Table 2-1. W83C553F Pins Listed by Pin Number 1 DRQ7 2 PWRGD 3 INIT 4 IGNNE#/HRESET# 5 PMACT#/ISARST 6 GNT4#/FLSHREQ# 7 REQ4#/FLSHACK# 8 PWRPC/X86#/CPUGNT# 9 CPUREQ# 10 INT 11 NMI 12 FERR#/IRQ13 13 PCI5TH#/GNT3# 14 VDD 15 REQ3# 16 ARBDIS#/GNT2# 17 REQ2# 18 INTD# 19 INTC# 20 INTB# 21 INTA# 22 A20M#/PCIRST# 23 PCICLK 24 VSS 25 REQ0#/PIBGNT# ...

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... W83C553F Note: Pins direction and assignment may not reflect exact pins , refers to exact pin description . Figure 2-2. W83C553F Logic Symbol Diagram WINBOND SYSTEMS LABORATORY Pin Descriptions 12 ...

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... W83C553F 2.2 Pin Descriptions This section describes the location and function of each pin on the W83C553F. Note the following conventions used in the tables: • Where more than one pin is listed for a signal, the first pin number corresponds to the most significant bit of the bus. For example, the Bus Command and Byte Enables bits (C/BE[3:0]#) use pins 1, 12, 22, and 31. • ...

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... Address Bit 20 Mask or PCI Reset. This multi-function pin functions as Address Bit 20 Mask when the W83C553F is in x86 mode, as determined by pin 8 strapping after power-up. It functions as PCI Reset when the W83C553F is in PowerPC mode driven for one millisecond duration after one of the following conditions: - PWRGD active edge ...

Page 18

... Input/ Device Select. This signal is asserted by the W83C553F when it is Output acting as a target in a transaction input when the W83C553F is acting as the initiator of a transaction. Input/ Stop. This is asserted to terminate the current transaction. It causes a ...

Page 19

... W83C553F under software control. Input/ PCI Interrupts. These PCI interrupts can be routed to the OD programmable interrupt controller inside the W83C553F under software control. Input PCI Lock. LOCK# is used to indicate an atomic operation that may require multiple transactions to complete. ...

Page 20

... PCI arbiter is disabled. This pin functions as REQ0# when the on-chip PCI arbiter is enabled. Output This is a multifunction pin. The W83C553F IDE master (Function 1) asserts this signal to request the use of the PCI bus when the on- chip PCI arbiter is disabled. This pin functions as GNT1# when the on-chip PCI arbiter is enabled, allowing PCI access to an external master ...

Page 21

... This multifunction pin is sampled by the W83C553F, following the Output PWRGD active edge 2.2K ohm resistor is weakly pulling this pin to VCC at this time, the W83C553F is in PowerPC mode weak pull down resistor is connected to ground, the chip is in x86 mode. When the PCI arbiter within the W83C553F is enabled (pin 16 ...

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... W83C553F Pin Name Pin # IDECS0 IDECS1#/ NAT/LEG# IDEIOWA# 85 IDEIORA# 83 IDEIOWB# 84 IDEIORB# 82 WINBOND SYSTEMS LABORATORY Table 2-4. IDE Interface Bus Signals Input/ Output Description Output Drive Chip Select 0. This signal is decoded from the AD bus to select both primary and secondary IDE Port Command Block Registers ...

Page 23

... W83C553F Pin Name Pin # IDEDRQA 97 IDEDAKA# 94 IDEDRQB 96 IDEDAKB# 93 DA[2:0] 88,90,89 DD[15:0] 98,101,103, 105,108, 110,112, 114,115, 113,111, 109,106, 104,102, 100 IDECHRDY 95 IDEIRQB 91 IDEIRQA 92 WINBOND SYSTEMS LABORATORY Table 2-4 (continued). IDE Interface Bus Signals Input/ Output Description Input DMA Request A. This signal is the primary port DMA handshake from the IDE device ...

Page 24

... W83C553F Pin Name Pin # BCLK 200 OSC 172 LA[23:17] 176,178, 180,182, 184,187, 189 SA[16:0] 144,145, 147-149, 151,152, 155,158, 160,162, 164,165, 167,169, 171,173 MASTER# 143 REFRESH# 150 MEMR# 141 MEMW# 142 WINBOND SYSTEMS LABORATORY Table 2-5. ISA Bus Signals Input/ Output Description Output ISA Bus Clock. ...

Page 25

... W83C553F Pin Name Pin # IOR# 140 IOW# 139 SMEMR# 138 SMEMW# 137 ZWS# 132 SBHE# 174 M16# 175 IO16# 177 IOCHK# 122 WINBOND SYSTEMS LABORATORY Table 2-5 (Continued). ISA Bus Signals Input/ Output Description Input/ I/O Read. Act as an output during PCI master and DMA cycles and Output as an input during ISA master cycles ...

Page 26

... W83C553F Pin Name Pin # IOCHRDY 135 BALE 168 AEN 136 TC 166 DRQ[7:5, 3:0] 1,203,198, 191,190, 193,196 DAK[2:0] 194,192, 195 IRQ[15, 14, 12:9, 186,188, 7:3] 183,181, 179,127, 154,157, 159,161, 163 WINBOND SYSTEMS LABORATORY Table 2-5 (Continued). ISA Bus Signals Input/ Output Description Input/ I/O Channel Ready. This signal is used by ISA slaves to extend the Output transfer cycle beyond the default ready timer expiration ...

Page 27

... Reset Drive bit set (Clock Divisor Register bit 3) ISA Reset is the inverted logical equivalent of PCI Reset. When the W83C553F is in x86 mode, this pin functions as Power Management Active the output signal to the CPU bridge which indicates the system activity status by becoming active when a break event has occurred ...

Page 28

... This is a multi-function pin. When the W83C553F is in PowerPC mode, this pin functions as the chip select for ports in the 800h- 8FFh I/O address range. When the W83C553F is in x86 mode, this pin functions as the upper bit of the X-bus Address. In x86 mode, an external decoder is required to decode the chip selects for X-bus ...

Page 29

... Output This multi-function pin functions as Ignore Numeric Error (IGNNE#) when the W83C553F is in x86 mode as determined by pin 8 strapping after reset. It functions as HRESET# when the W83C553F is in PowerPC mode. For connection to the PowerPC, HRESET# is asserted for a duration of one millisecond after one of the following events: ...

Page 30

... W83C553F Pin Name Pin # VSS 24,38,48, 68,80, 107,124, 146,156, 170,201 VDD 14,32,45, 70,99,153,185 WINBOND SYSTEMS LABORATORY Table 2-8. Power and Ground Signals Input/ Output Description - These 11 pins are connected to the power supply ground. All VSS pins must be connected for proper device operation. - These 7 pins are connected to the power supply +5V. All VDD pins must be connected for proper device operation ...

Page 31

... ISA Bus is secondary I/O bus The W83C553F accepts cycles from the PCI bus and translates them onto the ISA bus. It also requests the PCI master bridge to generate PCI cycles on behalf of IDE DMA or an ISA master. The ISA bus interface thus contains a standard ISA Bus Controller and data buffering logic ...

Page 32

... The W83C553F has two basic operational states: reset and active. The reset state brings all internal logic to a known state, and configures some chip features. The active state is the normal operating state that allows software to perform chip configuration, access to the PCI and ISA register sets, and accessing four IDE devices ...

Page 33

... W83C553F->PCI address/data, W83C553F- >Latched & ISA address ISA refresh W83C553F->ISA address WINBOND SYSTEMS LABORATORY Address Bus Path ISA data->W83C553F->PCI address/data PCI address/data->W83C553F ->ISA data PCI address/data->W83C553F ->ISA data ISA data->W83C553F->PCI address/data Electrical Specifications ...

Page 34

... IRDY# to the PCI bus if the targeted memory is not on the ISA side. Addresses and commands are valid during the address phase, while PAR is asserted one clock later. The W83C553F always activates FRAME# for 2 PCLKs because it does not conduct bursting cycles for PCI-to-ISA reads or writes. ...

Page 35

... I/O read or bus master memory write cycle) or checked (slave I/O write or bus master memory read cycle) on the next rising clock edge. The W83C553F will report data parity errors on slave I/O write cycles it claims (by the assertion of DEVSEL#) and bus master memory write cycles via the PERR# signal when enabled. ...

Page 36

... W83C553F Refer to Figure 3-1. Bus acquisition timing cycles are defined by the C/BE[3:0]# command lines during the address (AD) phase of each PCI cycle. WINBOND SYSTEMS LABORATORY Figure 3-1. Bus Acquisition Timing Electrical Specifications 33 ...

Page 37

... W83C553F internal bus master registers, IDE device, and ISA registers or X-bus registers single, non-burst 32-bit transfer cycle, initiated by the CPU fixed duration, i.e. the W83C553F will assert TRDY# on the 4th bus cycle of the transfer when accessing the internal bus master registers. It will have a variable duration when accessing an IDE device or ISA register ...

Page 38

... W83C553F internal bus master registers, IDE device, and ISA registers or X-bus registers single, non-burst 32-bit transfer cycle, initiated by the CPU fixed duration, i.e. the W83C553F will assert TRDY# on the 4th bus cycle of the transfer when accessing the internal bus master registers. It will have a variable duration when accessing an IDE device or ISA register ...

Page 39

... Refer to Figure 3-4. The Slave Configuration Read command cycle is used by the host processor to read the PCI configuration space in the W83C553F. This provides the processor with device information single, non-burst 32-bit transfer, of fixed duration, i.e. the W83C553F will assert TRDY# on the 4th bus cycle of the transfer. Figure 3-4. Slave Configuration Read Timing ...

Page 40

... Refer to Figure 3-5. The Slave Configuration Write command cycle is used by the host processor to write the PCI configuration space in the W83C553F. This permits the processor to control basic W83C553F activity, such as enable/disable, change I/O location, etc single, non-burst 32-bit transfer, of fixed duration, i.e. the W83C553F will assert TRDY# on the 4th bus cycle of the transfer ...

Page 41

... PCI REQ# for the bus and, when PCI GNT# is asserted, reads one Dword from system memory. The bus is then released. The data phase in Figure 3-6 takes two clock cycles, as determined by TRDY#. The W83C553F activates all byte enables, even if some byte lanes do not contain valid data. It internally discards unnecessary bytes. ...

Page 42

... The Master Memory Write command (C/BE[3:0 during the address phase) cycle is used by the W83C553F when writing to memory. The W83C553F issues a request for the bus and, when granted access, writes one Dword to system memory. The bus is then released. The data phase in Figure 3-7 takes two clock cycles, as determined by TRDY#. ...

Page 43

... Cache Line Size Register. In Figure 3-8, the W83C553F issues a request for the bus and, when access is granted, reads eight Dwords from system memory before releasing the bus. All data phases in this figure take one clock cycle, as determined by TRDY#. ...

Page 44

... FRAME# and IRDY# are de-asserted, indicating an IDLE cycle. When the W83C553F is a bus master, its PCI bus cycles may be terminated by the target as a Disconnect With Data Transfer, Disconnect Without Data Transfer, or Target Abort. The W83C553F's PCI bus cycles may also be terminated by the W83C553F itself as a Preemption or a Master Abort ...

Page 45

... STOP# is asserted without TRDY# being asserted at the same time. The W83C553F terminates the current transfer with de- assertion of FRAME#, and the de-assertion of IRDY#, at which point it releases the bus. The W83C553F will re-request the bus after two clock cycles if more data transferred. The starting address of the new transfer will be the address of the next untransferred data (i ...

Page 46

... W83C553F cannot recover from a target abort event. Any on-going IDE activity will be stopped immediately, and an interrupt will be generated if enabled. Abort and Error bits in the DMA Status register will be set. The PCI Configuration registers will not be cleared. The PCI Configuration Space Status Register's RTA bit will be set to indicate the W83C553F has received a Target Abort. ...

Page 47

... PCI Preemption Timing The main arbiter can void the PCI GNT# signal sent to the W83C553F, if the current bus cycle takes too long the case of DMA bursts. When PCI GNT# is removed, and the value in the Latency Timer Register has reached zero, the W83C553F will finish the current transfer, and immediately release the bus ...

Page 48

... PCI Master Abort Timing A Master Abort sequence is initiated by the W83C553F to abort its cycle if DEVSEL# is not asserted within four clocks after FRAME# is asserted. This sequence is treated as a fatal error. Any IDE activity will be terminated immediately. An NMI will be generated if programmed in register 40h, bit 0 (page 58.) The DMA Status Register's Abort and Error bits will be set. ...

Page 49

... For multiword DMA transfers, the IDEIOW[A:B]# or IDEIOR[A:B]# signal will free run at the programmed rate as long as DRQ remains asserted and the W83C553F is prepared to complete a data transfer. If IDEDRQ[A:B] has not de- asserted by the rising edge of the IDEIOW[A:B]# or IDEIOR[A:B]# signal multiword DMA is assumed and at least one more cycle will be executed ...

Page 50

... W83C553F will setup the proper address and chip selects. Once the address setup time has been met, IDEIOR[A:B]# or IDEIOW[A:B]# will be asserted and held on until the on command time has been met. The W83C553F will then de-assert IDEIOR[A:B]# or IDEIOW[A:B]# and hold the addresses and chip selects stable. If read ahead or posted writes are enabled for this device, read or write cycles will be executed at the programmed on/off timing until the read ahead buffer is full, the read ahead count is complete, or the posted write buffer is empty ...

Page 51

... W83C553F 3.17 32-Bit Data Transfers 32-bit data transfers are used to reduce system overhead and improve performance. The standard PIO protocol requires the system CPU to execute an I/O cycle and a memory cycle to move two bytes of data between the IDE device and memory. To transfer 4 bytes of data would require two I/O cycles and two memory cycles. This can be accomplished with one 32-bit I/O and one 32-bit memory cycle ...

Page 52

... When operating as a bus master on the PCI bus, DMA cycles will be executed on the IDE interface. In this mode, once the BMEN bit of the Bus Master Control Register is set the W83C553F will de-assert the chip selects for that port and respond to DRQ as defined above interrupt is generated on the IDE interface, it will be delayed for IDE device to memory transfers until the FIFO is empty (written to memory) ...

Page 53

... When in the active state, the eight masters supported by the W83C553F are its two internal masters (ISA bridge and IDE), the system CPU, and REQ#/GNT#[4:0] which are available to the system designer. The PCI5TH# function of pin 13 can be used to change the fifth REQ#/GNT# pair (on pins 6 and 7) to FLSHREQ#/FLSHACK# if desired (in either CPU mode) ...

Page 54

... It can be seen from the above table (and the respective pin descriptions on pages 12-25) that the W83C553F is able to generate all of the required reset signals for the microprocessor, PCI bus, and ISA bus when in PowerPC (non-x86) mode. WINBOND SYSTEMS LABORATORY x86 Function ...

Page 55

... W83C553F 4.0 REGISTER INFORMATION The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. The registers summarized in this section are organized as follows: • PCI Configuration Space - ISA Bridge Registers (Function 0) • ...

Page 56

... W83C553F W83C553F Register Accessibility Functional Block Config. Space PIC 1 Counter/Timer Port B RTC Index (shadow) DMA Page Port 92 PIC2 Co-processor Error DMA1 BMTR DMA2 Interrupt Mode RTC CMOS RAM X = accessible in x86 mode P = accessible in PowerPC mode WINBOND SYSTEMS LABORATORY Address Range (Hex) 0-FF 20-21 40- write ...

Page 57

... W83C553F 4.1 PCI Configuration Space - ISA Bridge Registers (Function 0) 4.1.1 Function 0 Header Registers Vendor ID Register (default = 10ADh) Bit Description: Bits [15:0]: VENDID. Vendor ID for Symphony Laboratories is 10ADh. Device ID Register (default = 0565h) Bit Description: Bits [15:0]: DEVID. Device ID for ISA bridge is 0565h. WINBOND SYSTEMS LABORATORY Electrical Specifications ...

Page 58

... Bit 6: Parity Error Response. This is a read/write bit. Bit 5: VGA Palette Snoop. W83C553F is not a VGA device. This read only bit is set to "0". Bit 4: Memory Write and Invalidate Enable. W83C553F does not generate memory write and invalidate commands. This read only bit is set to "0". ...

Page 59

... UDF Supported (UDFS). W83C553F does not support user definable features. This read only bit is set to "0". Bit 5: 66 MHz Capable (PCI66C). W83C553F does not support 66 MHz bus speed. This read only bit is set to "0". Bits [4:0]: Reserved. This read only bit is set to "0". ...

Page 60

... Bits [7:0]: PROGIF. Programming Interface is 00h. Header Type Register (default = 80h) Bit Description: Bit 7: MFCN. Multi-Function Device is "1". W83C553F contains two functions (ISA bridge and IDE master). Bits [6:0]: CFGLAY. Configuration Layout is 00h. Non-PCI-to-PCI bridge device. WINBOND SYSTEMS LABORATORY Electrical Specifications ...

Page 61

... Reserved. This read only bit is set to "0". Bit 6: Reserved. Bit 5: IAE. Interrupt Acknowledge Enable. Setting this bit allows the W83C553F chip to respond to the interrupt acknowledge command. This bit is active after reset. Bit 4: Reserved. This read only bit is set to "0". ...

Page 62

... W83C553F Scatter/Gather Relocation Base Address Register (default = 04h) Function: The value programmed into this register determines the high order I/O adress of the Scatter/Gather Command Registers, Scatter/Gather Status Registers, and Scatter/Gather Descriptor Table Registers. The first Scatter/Gather register default address is at 0410h. Type: ...

Page 63

... W83C553F Line Buffer Control Register (default = 00h) Type: Read/Write Bit Description: Bits [7:4]: Reserved. Bits [3:2]: ISA Master Line Buffer Configuration. Bit Bits [1:0]: DLBC. DMA Line Buffer Configuration. Bit IDE Interrupt Routing Control Register (default = EFh) ...

Page 64

... W83C553F PCI Interrupt Routing Control Register (default = 0000h) Type: Read/Write Bit Description: Bits [15:12]: INTARCH [3:0]. INTA# Routing Channel. This field specifies the routing channel for INTA#. Note channels and 13 are reserved. Setting this field to these values will disable routing. Default value after a hardware reset is "0". ...

Page 65

... Read/Write Function: The base address for the BIOS Timer Register located in PCI I/O space. The BIOS Timer resides in the W83C553F and is the only internal resource mapped to PCI I/O space. Bit Description: Bits [15:2]: BTMRBA. BIOS Timer Base Address. This register specifies the Base Address 15:2 for the BIOS Timer register located in the I/O space ...

Page 66

... W83C553F ISA-to-PCI Address Decoder Control Register (default = 01h) Type: Read/Write Bit Description: Bits [7:4]: IPATOM [3:0]. Top of Main Memory. Defines the top of memory for ISA memory space. ISA memory accesses from 1 MByte to top of memory (except "hole") and above 16 MByte are forwarded to the PCI bus. ...

Page 67

... W83C553F ISA ROM Address Decode Enable Register (default = 00h) Function: When a bit is set to "1", memory accesses to the corresponding address range in the add-on BIOS area are forward to the PCI bus. Type: Read/Write Bit Description: Bit 7: MBEDC. Memory Block Enable; 880-896 KByte. (DC000-DFFFFh). ...

Page 68

... W83C553F ISA-to-PCI Memory Hole Start Address Register (default = 00h) Type: Read/Write Bit Description: Bits [7:0]: IPAHA. Memory Hole Start Address. These 8 bits specify the 8 most significant bits of the ISA address: LA[23:16]. Bit 7 Bit 6 LA23 LA22 ISA-to-PCI Memory Hole Size Register (default = 00h) ...

Page 69

... W83C553F Clock Divisor Register (default = 00h) Type: Read/Write Bit Description: Bits [7:4]: Reserved. Bit 3: RSTDRV. Reset Drive, valid only in PowerPC mode. When this bit is set, PCIRST# and ISARST are enabled for 1 ms. This bit then clears (resets) itself. Bits [2:0]: Clock select (CLKSEL). This field selects the divisor for generating BCLK from PCICLK. ...

Page 70

... W83C553F Chip Select Control Register (default = 33h) Type: Read/Write Bit Description: Bit 7: EBIOSCSE. Extended BIOS Enable. 0= Disabled 1= Memory access from FFF80000h to FFFDFFFFh will assert ROMCS in PowerPC mode or the encoded output XCS[1 x86 mode. Bit 6: LBIOSCSE. Lower BIOS Enable. 0= Disabled 1= Memory access from FFFE,0000h to FFFE,FFFFh or FFEE,0000 to FFEE,FFFF or 000E,0000 to 000E,FFFF will assert ROMCS in PowerPC mode or the encoded output XCS[1: x86 mode ...

Page 71

... W83C553F AT System Control Register (default = 04h) Type: Read/Write Bit Description: Bit 7: Reserved. Bit 6: ISA Refresh Enable. Bit 5: Reserved, always 0. Bit 4: FERR# Enable. If this bit is set to "1," pin 12 will function as the Numeric Co-processor error input. Bit 3: Reserved. Bit 2: P92E. Port 92 Enable. When enabled, access to Port 92 is enabled. When disabled, cycle will be passed to the ISA bus ...

Page 72

... W83C553F AT Bus Control Register (default = 00h) Type: Read/Write Bit Description: Bits [7:3]: Reserved. Bit 2: I/O Recovery Time normal BCLK delay for 16-bit I/O and 8 BCLK for 8-bit I/O access Bit 1: Extended ALE disable 1 = enable Bit 0: Reserved. WINBOND SYSTEMS LABORATORY Electrical Specifications 69 ...

Page 73

... W83C553F IRQ Break Event Enable 0 Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: IRQ7. Enable IRQ7 as Break Event. When this bit is "1," IRQ7 as Break Event detection is enabled ...

Page 74

... W83C553F IRQ Break Event Enable 1 Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: IRQ15. Enable IRQ15 as Break Event. When this bit is "1," IRQ15 as Break Event detection is enabled ...

Page 75

... W83C553F Additional Break Event Enable Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: Reserved. Bit 6: PCI SERR#. SERR Detection Enable. When this bit is "1," SERR detection is enabled. Upon detection, the PMU will de-assert PMACT# ...

Page 76

... W83C553F DMA Break Event Enable Register (default = 00h) Function: This power management register may only be used while the W83C553F is in x86 mode. Type: Read/Write Bit Description: Bit 7: DRQ7. Enable DRQ7 as Break Event. When this bit is "1," DRQ7 detection is enabled. Upon activation, the PMU will de-assert PMACT# ...

Page 77

... W83C553F Level 1 Arbiter There are two control bits for bank 1,2,3 modules. The "pfix" bit determines the fixed priority of the bank. The "protat" bit determines whether to rotate the priority scheme of the bank after a grant is given. If the "protat" bit is not set, the arbiter will give one request line higher priority ALL THE TIME. If the " ...

Page 78

... W83C553F Function: These register locations are reserved. Software should not attempt to read or write these locations. PCI Arbiter Priority Control Register 1 (default = E0h) Type: Read/Write Bit Description: Bits [7:5]: Bank [3:1] Rotate Enable. Defaults to 111b (enabled). Bits [4:3]: Bank 4 Fixed Mode Priority Select. Bit ...

Page 79

... W83C553F PCI Arbiter Priority Extension Control Register PCI Arbiter Priority Extension Control Register (default = 01h) Type: Read/Write Bit Description: Bits [7:4]: Reserved Bits [3:1]: Super Agent Select [2:0]. 000 DISABLE 001 IDEIRQ# 010 SIOIRQ# 011 CPUREQ# Bits 0: Bank 4 Rotate Enable. Defaults to 1b (enabled). PCI Arbiter Priority Enhanced Control Register (default = 00h) ...

Page 80

... W83C553F PCI Arbiter Control Register (default = 80h) Type: Read/Write Bit Description: Bit 7: GAT. Guaranteed Access Timing. If set to a 1b, this bit enables Function 0 Flush Request and Flush Acknowledge operation on pins 6 and 7 (provided pin 13 is not pulled low after reset). This bit defaults to a 1b. ...

Page 81

... W83C553F 4.2 ISA Bridge (Function 0) I/O Registers 4.2.1 DMA Controller I/O Registers Base and Current Address Register Type: Read/Write Bit Description: Bits [15:0]: Base and Current Address. Access by two consecutive cycles. Internal high/low byte pointer toggles after each access. Base and Current Word Count Register Type: ...

Page 82

... W83C553F DMA Command Register (default = 00h) Type: Write only Bit Description: Bit 7: Reserved. Bit 6: DRQ Active Level. When this bit is "0" (default), DRQ is active high. When this bit is "1," DRQ is active low. Bit 5: Reserved. Extended/Late Write Select. Must be "0". ...

Page 83

... W83C553F DMA Controller 1 Status Register (default = 00h) Type: Read only Bit Description: Bit 7: Channel 3 Request. Bit 6: Channel 2 Request. Bit 5: Channel 1 Request. Bit 4: Channel 0 Request. Bit 3: Channel 3 Terminal Count. Bit 2: Channel 2 Terminal Count. Bit 1: Channel 1 Terminal Count. Bit 0: Channel 0 Terminal Count. WINBOND SYSTEMS LABORATORY ...

Page 84

... W83C553F DMA Controller 2 Status Register Type: Read only Bit Description: Bit 7: Channel 7 Request. Bit 6: Channel 6 Request. Bit 5: Channel 5 Request. Bit 4: Reserved. Cascade for DMA Controller 1. Bit 3: Channel 7 Terminal Count. Bit 2: Channel 6 Terminal Count. Bit 1: Channel 5 Terminal Count. Bit 0: Reserved. Cascade for DMA Controller 1. ...

Page 85

... W83C553F DMA Controller Request Register Type: Write only Bit Description: Bits [7:3]: Reserved. Bit 2: Set Request. Bits [1:0]: Channel Select. DMA Controller Mask Register Type: Write only Bit Description: Bits [7:3]: Reserved. Bit 2: SETMASK. Set Mask bit. Bits [1:0]: CSEL [1:0]. Channel Select bits. WINBOND SYSTEMS LABORATORY ...

Page 86

... W83C553F DMA Controller Mode Register Type: Write only Bit Description: Bits [7:6]: Transfer Mode. Bit 7 Bit Bit 5: Decrement Address. When set to "1", address pointer is decremented after each transfer. Default is incrementing address. Bit 4: Auto initialize Enable. Bits [3:2]: Transfer Type ...

Page 87

... W83C553F Clear Byte Pointer Register Type: Write only Bit Description: Bits [7:0]: Clear Byte Pointer. Writing any pattern in this register will reset the byte pointer for the Base and Current Address/Data registers. Master Clear Register Type: Write only Bit Description: Bits [7:0]: Master Clear ...

Page 88

... W83C553F Clear Mask Register Type: Write only Bit Description: Bits [7:0]: Reserved. Writing this register will clear the mask bits of all channels. Write All Mask Register (default = 0Fh) Type: Write only Bit Description: Bits [7:4]: Reserved. Bit 3: Channel 3 Bit 2: Channel 2 Bit 1: Channel 1 Bit 0: ...

Page 89

... W83C553F Memory Page Register (default = 00h) Type: Read/Write Bit Description: Bits [7:0]: Memory Address [23:16] for DMA cycles. Reserved Page Register Bit Description: Bits [7:0]: Reserved. Software should not attempt to access these registers. WINBOND SYSTEMS LABORATORY Electrical Specifications 86 ...

Page 90

... W83C553F Extended Mode Register (default = 0xh) Type: Write only Bit Description: Bits [7:6]: Reserved. Bits [5:4]: Timing. Bit 5 Bit Bits [3:2]: Reserved. Bits [1:0] DMAC[1:0] Channel Select. Bit 1 Bit DMA Page Registers (default = 00h) Type: Read/Write Bit Description: Bits [7:0]: AD[31:24]. WINBOND SYSTEMS LABORATORY ...

Page 91

... W83C553F WINBOND SYSTEMS LABORATORY Electrical Specifications 88 ...

Page 92

... W83C553F Scatter/Gather Registers Scatter/Gather (S/G) provides the capability of transferring multiple buffers between memory (ISA/PCI) and I/O (ISA DMA device) without CPU intervention. In Scatter/Gather the DMA can read the memory address and word count from an array of buffer descriptors located in system memory (PCI only), called the Scatter/Gather Descriptor (SCD) table. This allows the DMA controller to sustain DMA transfers until all of the buffers in the SGD table are transferred ...

Page 93

... W83C553F Scatter/Gather Interrupt Status Register Scatter/Gather Interrupt Status Register (default = 00h) Type: Read only Bit Description: Bits [7:5]: Channel [7:5] Interrupt Status. When one of these bits is set to a 1b, Channels 7 through 5 have an interrupt due to a Scatter/Gather transfer; otherwise these bits are set to 0b. Bit [4] ...

Page 94

... W83C553F Scatter/Gather Command Registers (default = 000000h) Function: Each of these three registers controls the Scatter/Gather operation of DMA channels [7:5]. Type: Write only Bit Description: Bit 7: IR13EOPSEL. IRQ13/EOP Select. If enabled via bit 6 of this register, bit 7 selects whether EOP or IRQ13 is asserted at termination caused by a last buffer expiring. If bit EOP is asserted ...

Page 95

... W83C553F Scatter/Gather Status Registers Type: Read only Bit Description: Bit 7: NEXT_LINK_NULL. Next Link Null Indicator. Bit 6: Reserved. Bit 5: ISSUE_IRQ13_EOP. Issue IRQ13 on last buffer. When bit EOP is issued on last buffer; when bit IRQ13 is issued. Bit 4: Reserved. Bit 3: SG_BASE_REQ_FULL. Scatter/Gather Base Register Status. When bit the base register is empty ...

Page 96

... W83C553F Scatter/Gather Descriptor Table Pointer Register Type: Read/Write Bit Description: Bits [31:0]: SG_TBL_PTR. The Scatter/Gather Descriptor Table Pointer Register contains a 32-bit pointer address to the main memory location where the software maintains the Scatter/Gather descriptors for the linked-list buffers. Bits [31:0] correspond to A[31:0] on the PCI AD bus. ...

Page 97

... Addresses 20h and A0h are referred to as the base address of Interrupt Controllers #1 and #2 respectively. An I/O write to the Interrupt Controller # base address, with bit 4 equal to "1," is interpreted as ICW1. For W83C553F based ISA systems, three I/O writes to "base address +1" must follow the ICW1 to perform writes to ICW2, ICW3 and ICW4. ...

Page 98

... W83C553F Operational Control Word 2 Register Function: The Operational Control Word 2 (OCW2) Register controls both the Rotate Mode, End of Interrupt Mode and combinations of the two. Type: Write Only Bit Description: Bits [7:5]: ROT, SELLEVEL and EOI. These three bits control the Rotate, End of Interrupt (EOI) Modes ...

Page 99

... W83C553F Operational Control Word 3 Register Function: The Operational Control Word 3 (OCW3) Register serves three functions. It enables special mask mode and controls poll mode and IRR/ISR register read. Type: Read/Write Bit Description: Bit 7: Reserved. This bit must be "0." Bit 6: SMM. Special Mask Mode. If ESMM and SMM are both "1," the interrupt controller enters SMM. If ESMM is " ...

Page 100

... W83C553F Initialization Command Word 2 Register Function: The Initialization Command Word 2 (ICW2) Register is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed into bits [7:3] is used by the host CPU to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller ...

Page 101

... W83C553F Initialization Command Word 3 Register - PIC 1 (Master, default = 04h) Function: On the Interrupt Controller #1 (the master controller), this register indicates which IRQ line physically connects the INT output of Interrupt Controller #2 (PIC 2) to Interrupt Controller #1 (PIC 1). Type: Write Only Bit Description: Bits [7:3]: SLAVE[7:3]. These bits must be programmed to " ...

Page 102

... Bit 3: BUF. Buffered Mode. This bit must be programmed to "0" for the W83C553F. Bit 2: MNS. Master/Slave in Buffered Mode. This bit must be programmed to "0" for the W83C553F. Bit 1: AEOI. Automatic End of Interrupt. This bit should normally be programmed to "0." If programmed to "1," Automatic End of Interrupt Mode is enabled. ...

Page 103

... W83C553F Operational Control Word 1 Register Function: The Operational Control Word 1 (OCW1) Register sets and clears the mask bits in the Interrupt Mask (IMR) Register. Each interrupt request line may be selectively masked or unmasked any time after initialization. Type: Read/Write Bit Description: Bits [7:0]: IMR[7:0]. When a " ...

Page 104

... W83C553F Interrupt Edge/Level Control Register (default = 00h) Type: Read/Write Bit Description: Bit 7: Controller 1-Channel 7. Controller 2-Channel 15. Bit 6: Controller 1-Channel 6. Controller 2-Channel 14. Bit 5: Controller 1-Channel 5. Controller 2-Channel 13; must be "0" for edge. Bit 4: Controller 1-Channel 4. Controller 2-Channel 12. Bit 3: Controller 1-Channel 3. Controller 2-Channel 11. ...

Page 105

... W83C553F 4.2.3 Counter/Timer I/O Registers Counter Register Function: These three registers contain the actual counter values programmed into counters 0 through 2. The set values are determined by selections made in the Timer Control Register (43h). Type: Read/Write Bit Description: Bits [7:0] C[15:8]/C[7:0]. Upper and lower counter values. WINBOND SYSTEMS LABORATORY ...

Page 106

... W83C553F Counter Status Register Function: Each counter's status byte can be read following a timer Read Back command, as programmed in the Timer Control Register (43h). Type: Read back Bit Description: Bit 7: OUT. Count Out Status. This bit indicates the Counter Out pin state. When set to "1", the OUT pin of the counter is also a " ...

Page 107

... W83C553F Timer Control Register Function: The Timer Control Register specifies the counter selection, operating mode, counter byte programming order and count value size, and whether the counter counts down in a 16-bit or Binary Coded Decimal (BCD) format. After writing the control word, a new count can be written at any time. The new value will take effect according to the programmed mode ...

Page 108

... W83C553F BIOS Timer Register (default = 00000000h) Function: After a counter value is written into the lower 16 bits of this register, it will decrement to 0 with every BCLK. Type: Default Bit Description: Bits [31:16]: Reserved. Bits [15:0]: BTMR. BIOS Timer. When a counter in written into this field, the counter will be decremented by 1 every BCLK until 0 is reached ...

Page 109

... W83C553F 4.2.4 Miscellaneous I/O Control Registers NMI Status and Control (Port B) Register (default = 00h) Type: Read/Write Bit Description: Bit 7: SERR# Status. Bit 6: IOCHK# Status. Bit 5: Timer Counter 2 Output. Bit 4: Refresh Cycle Toggle. Bit 3: IOCHK# NMI Enable. Bit 2: SERR# NMI Enable. Bit 1: Speaker Data Enable. ...

Page 110

... W83C553F NMI Enable and RTC Address Register (default = 0xxx, xxxx) Type: Shadow Bit Description: Bit 7: NMI Enable. Bits [6:0]: RTC Address. WINBOND SYSTEMS LABORATORY Electrical Specifications Share 107 ...

Page 111

... W83C553F Port 92 Register (default = 24h) Type: Read/Write Bit Description: Bits [7:3]: Reserved. These bits default to "00100." Bit 2: Read only. Value of pin 116 after reset. See page 25. Bit 1: Alt A20. Bit 0: Hot Reset. Changing this bit from will cause a system soft reset to occur. This bit must be returned to 0 before another soft reset can be issued ...

Page 112

... W83C553F RTC CMOS RAM Protect 1 Register Type: Write only Bit Description: Bits [7:0]: Any value. Writing any value to this port sets a flip-flop which prevents any subsequent access to addresses 20h - 2Fh of the Real Time Clock address space. This flip-flop is cleared only on power-on reset. A read has no effect. This register's initial state after reset is in unprotected mode ...

Page 113

... W83C553F 4.3 PCI Configuration Space - Bus Master IDE Registers (Function 1) The configuration space is organized as 64 double word (32-bit) registers divided into two sections, the PCI specified and defined Header registers and the Control registers. Header registers are located in the first 16 double words. Control registers are located in the last 48 double words ...

Page 114

... All reserved bits and bytes return a logic 0 when read. All reserved bytes written will execute normal PCI cycles, but will not affect the operation or device registers. Internal register information for the W83C553F SIO is organized as follows: • Register name and Index value offset from base address. ...

Page 115

... W83C553F 4.3.1 Function 1 Header Registers The registers contained in this address space are defined and required by the PCI Specification Revision 2.1. Six fields in the pre-defined header deal with device identification. These fields are Vendor ID, Device ID, Revision ID, Header Type, Class Code, and Programming Interface and their addresses are 00h-03h,08h-0Bh. ...

Page 116

... PARITY. This is the enable bit for the PERR# output driver. When bit 1b, slave write data parity errors, and master memory read data parity errors, will be reported on PERR#. Write data parity errors are only reported for bus cycles claimed by the W83C553F (DEVSEL# asserted). Bit after a reset. ...

Page 117

... This bit is not used and is hardwired to a logic 0. Bit 2: BMEN. This bit must be set to allow the W83C553F to perform bus master cycles. Writing this bit will set it. Also, writing bit 0 (Start/Stop Bus Master) of the Primary or Secondary Bus Master IDE Command Register will set this bit. This bit after a reset. ...

Page 118

... Bit Description: Bit 15: PE. This bit is set anytime a parity error is detected during a slave data write to the W83C553F, for any command phase parity error, or when operating as a bus master for any memory read parity error. The function of this bit is not affected by the Device Control Register parity bit. ...

Page 119

... This will maximize the PCI bus bandwidth for PIO data transfer cycles. Bit 8: MPE. This bit will be set when operating as a bus master and either the PERR# output is driven low by the W83C553F or the target asserts PERR# and bit 6 of the Device Control Register is set. Bit 7: FBB ...

Page 120

... W83C553F Revision ID Register (default = 05h) Function: This register specifies a device specific revision identifier. The first Symphony bus master device was 01h with subsequent bus master IDE chips being 02h, 03h, etc. This specification is written to define device revision 05h. Type: Read only ...

Page 121

... W83C553F Programming Interface Register ( Default = 8Ah) Function: There are no PCI predefined configuration register sets released for this class of device but the PCI SIG has generated two proposed interfaces which are both supported. The first interface defines native and legacy IDE devices and is described in PCI Rev. 2.1 spec. The Programming Interface register will support both the native and legacy modes ...

Page 122

... The programmed value effects the memory read and write commands executed when the W83C553F is operating as a bus master. The default value is 08h. This register can only be programmed to 04h (16 bytes), 08h (32 bytes), or 00h (4 bytes); all other values will be ignored ...

Page 123

... W83C553F Latency Timer Register (default = 00h) Function: This register specifies, in PCI bus clocks, the value of the latency timer when operating as a bus master. Bits 0 through 2 are hardwired to a 0b. Bits 3 through 7 are programmable allowing a programmable latency value in increments of 8 PCI clocks. The result is a timer granularity of eight clocks. This register has a default value of 00h ...

Page 124

... This means that register accesses to 3F4h, 3F5h, 3F7h, 374h, 375h or 377h (or the equivalent offset) will not be claimed or executed. The W83C553F will only decode IDE port addresses if the IOEN bit of the Device Control Register is high and the IDE port is enabled in the W83C553F function 1: IDE Control/Status Registers. ...

Page 125

... This Base Address Register is used to define the I/O address of the Bus Master IDE Register set in systems which use multi- word DMA mode disk drives. This register set is internal to the W83C553F but is located in the I/O address space instead of the Configuration address space. The default value of Base Address Register 4 is 00000001h. When programmed with a value of FFFFFFFFh, a value of FFFFFFF1h will be read back indicating a required address range of 16 bytes ...

Page 126

... The Min Grant is the time required to complete a worst case burst assuming a 33MHz PCI clock. The hard coded value is 02h which represents 0.5µs. The Max Latency specifies how often the W83C553F needs to gain control of the PCI bus. The hard coded value is 28h which represents 10µs. ...

Page 127

... These configuration registers control various features of the W83C553F and the IDE interface. Reserved registers are hardwired to a 00h and cannot be programmed. The first register controls the general features of the W83C553F and both IDE ports. The next four registers control the features and timing of the 4 individual IDE devices. All features of the IDE interface that have no effect on the performance of the mass storage subsystem have been set to fixed values in hardware (i.e. ...

Page 128

... W83C553F IDE Control/Status Register Function: This register controls the two IDE ports of the W83C553F. Type: Read/Write WINBOND SYSTEMS LABORATORY Electrical Specifications 125 ...

Page 129

... W83C553F Bit Description: Bit 31: Reserved. This bit is hardwired to 0b. Bit 30: IDE_IRQB. This is the IDE_IRQB input signal. It reflects the unbuffered state of the IDE_IRQB input. Bit 29: Reserved. This bit is hardwired to 0b. Bit 28: IDE_IRQA. This is the IDE_IRQA input signal. It reflects the unbuffered state of the IDE_IRQA input ...

Page 130

... W83C553F Port x Drive x Control Registers Function: These registers control the features of the four devices connected to the two ports. All four registers are identical and control the features of only one device. The Port 0 Drive 0 Control Register (44h-47h) controls the features of the master drive attached to the primary port. The Port 0 Drive 1 Control Register (48h-4Bh) controls the features of the slave drive attached to the primary port ...

Page 131

... Bits [31:24]: Reserved. These bits are hardwired to a 0b. Bits [23:16]: User Defined. These bits are read/write and do not affect the operation of the W83C553F. They can be used by the driver as a temporary storage. These bits will be 0b after reset. Bits [15:13]: Reserved. These bits are hardwired to a 0b. ...

Page 132

... W83C553F Table 4-4. Programming CMD ON and CMD OFF Times Drive Operation Cycle Time / Mode DIOR#/DIOW# 16-bit (minimum) PIO Mode 0 600ns/165ns PIO Mode 1 383ns/125ns PIO Mode 2 240ns/100ns PIO Mode 3 PIO Mode 4 PIO Mode 5 (proposed) Single Word DMA 960ns/480ns Mode 0 Multiword DMA 480ns/215ns ...

Page 133

... W83C553F 4.4 Bus Master IDE (Function 1) I/O Registers The Bus Master IDE Register set is defined by the PCI SIG composed of 16 8-bit registers and is located at the I/O address specified by Base Address Register 4. The registers can be accessed 8, 16, 24 bits at a time. This register set is supplied to offer a higher performance lower overhead IDE disk protocol. With this protocol, the host (PCI) transfers will be bus master cycles and the IDE device transfers will be DMA ...

Page 134

... W83C553F 4.4.1 Primary/Secondary Command Registers Primary/Secondary Command #1 Registers Function: These registers are used to control DMA data transfers to/from the two IDE ports when multi-word DMA disk drives are used. Type: Read/Write Bit Description: Bits [7:4]: These bits are hardwired to 0b. Bit 3: W/R#. This bit controls the bus master transfer direction. Low is PCI memory to IDE device and high is IDE device to PCI memory ...

Page 135

... This bit after a reset. Bit 5: MDC. Master drive DMA capable is a status bit that is set by a driver/application to indicate that the master drive on the indicated port is DMA capable and that the W83C553F. is initialized for optimal performance. This bit after a reset. Bit [4:3]: These bits are hardwired ...

Page 136

... These registers contain the starting address of the first Physical Region Descriptor Table in memory which applies to cases where the W83C553F is functioning as a PCI bus master with one or more multi-word DMA mode disk drives. Bits 31 through 2 define a double word aligned address in memory. Bits 1 and 0 are reserved and will be ignored on writes and read as 00b ...

Page 137

... W83C553F 5.0 ELECTRICAL SPECIFICATIONS This section contains all electrical specifications for Winbond Systems Laboratory W83C553F SIO chip. The W83C553F must meet all absolute maximum ratings to avoid being damaged; and all combinations of the AC, DC and recommended operating specifications. Parameter Storage Temperature Supply Voltage (Vdd) ...

Page 138

... W83C553F Table 5.3. DC Characteristics (Ta=0°C to 70°C, Vdd=5V+/ -5%) Parameter Input low level Input high level Output low voltage: 4mA buffer, IOL=4mA 8mA buffer, IOL=8mA 12mA buffer, IOL=12mA 16mA buffer, IOL=16mA Output high voltage: 4mA buffer, IOL=4mA 8mA buffer, IOL=8mA 12mA buffer, IOL=12mA ...

Page 139

... W83C553F 6.0 TIMING DIAGRAMS This chapter lists the following PCI, ATA, and ISA timing information: • PCI Clock Timing • PCI Bus Timing • IDE Interface Timing • IDE Data Transfer Timing • Miscellaneous Timing • Example PIO ATA Data Transfer Timing • ...

Page 140

... W83C553F 6.1 PCI Timing Diagrams This section provides timing information on PCI cycles supported by the W83C553F. Note: For 5V PCI Bus, measurements were taken from 0.4V to 2.4V. All V DD are 4.75V to 5.25V Parameter t1 CLK cycle time t2 CLK high time t3 CLK low time t4 CLK slew rate WINBOND SYSTEMS LABORATORY Table 6-1 ...

Page 141

... W83C553F Note: For 5V PCI Bus, measurements were taken from 0.4V to 2.4V. All V DD are 4.75V to 5.25V Parameter t5 Setup to CLK rising t6 Hold from CLK rising WINBOND SYSTEMS LABORATORY Table 6-2. PCI Bus Timing Values Min Max 7ns - All PCI bussed signals, except REQ# and GNT#. ...

Page 142

... W83C553F Parameter t7 Setup to CLK rising t8 Valid from CLK rising t9 Float from CLK rising WINBOND SYSTEMS LABORATORY Table 6-2 (continued). PCI Bus Timing Values Min Max 10ns - Timing for GNT#. 12ns - Timing for REQ#. 2ns 11ns All PCI bussed signals, except REQ# and GNT# ...

Page 143

... W83C553F Parameter t11 Address Setup to command low t12 Address hold from command high t13 IDE_IOCHRDY high setup to command high t14 Read data setup to IDE_IOR# high t15 Read data hold from IDE_IOR# high t16 Write data setup to IDE_IOW# high t17 Write data hold from IDE_IOW# high ...

Page 144

... W83C553F Parameter t20 IDEDRQ[A:B] high to IDEDAK[A:B]# low delay t21 IDEDAK[A:B]# setup to command low t22 CS0#, CS1# setup to command low t23 IDEDAK[A:B]#, CS0#, CS1# hold from command high WINBOND SYSTEMS LABORATORY Table 6-4. IDE Data Transfer Timing Min 0ns 0ns 3 x t1ns t1ns ...

Page 145

... W83C553F Parameter t24 IDEIRQ[A:B] high to INT# low or ISA IRQ high t25 IDEIRQ[A:B] low to INT# float or ISA IRQ low t26 RST# low to IDE_RST# low t27 RST# high to IDE_RST# high t28 IDECS1# setup to RST# high t29 IDECS1# hold from RST# high. WINBOND SYSTEMS LABORATORY Table 6-5 ...

Page 146

... W83C553F 6.2 IDE/ATA Data Transfers This information has been transferred from the ATA-2 x3T9.2 specification for PIO modes 0-3, Multiword DMA modes 0-1 and Single-word DMA modes 0-2. SFF 8033 Rev. 0.2 defines PIO mode 4 and Multiword DMA mode 2. 6.2.1 Example PIO ATA Data Transfer Timing Parameter ...

Page 147

... W83C553F Table 6-6 (continued). PIO ATA Data Transfer Timing Parameter t2 IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0 16-bit t2 Pulse Width 8-bit t2i IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0 recovery time t3 IDEIOW[A:B]# data setup t4 IDEIOW[A:B]# data hold WINBOND SYSTEMS LABORATORY Values Min Max 165ns t0 is the minimum total cycle time the ...

Page 148

... W83C553F Table 6-6 (continued). PIO ATA Data Transfer Timing Parameter t5 IDEIOR[A:B]# data setup t6 IDEIOR[A:B]# data hold t6z IDEIOR[A:B]# data tri-state t9 IDEIOR[A:B]# / IDEIOW[A:B]# to address valid hold tR Read data valid to IDECHRDY active WINBOND SYSTEMS LABORATORY Values Min Max Mode 0 50ns Mode 1 35ns Mode 2 20ns ...

Page 149

... W83C553F 6.2.2 Example Single Word DMA ATA Data Transfer Timing Table 6-7. Single Word DMA ATA Data Transfer Timing Parameter t0 Cycle Time tC IDEDAK[A:B]# to IDEDRQ[A:B] delay tD IDEIOR[A:B]# / IDEIOW[A:B]# 16-bit minimum command active time tE IDEIOR[A:B]# data access WINBOND SYSTEMS LABORATORY Values Min Max Mode 0 960ns ...

Page 150

... W83C553F Table 6-7 (continued). Single Word DMA ATA Data Transfer Timing Parameter tF IDEIOR[A:B]# read data hold tG IDEIOW[A:B]# write data setup tH IDEIOW[A:B]# write data hold tI IDEDAK[A:B]# to IDEIOR[A:B]# / IDEIOW[A:B]# setup tJ IDEIOR[A:B]# / IDEIOW[A:B]# to IDEDAK[A:B]# hold tS IDEIOR[A:B]# read setup WINBOND SYSTEMS LABORATORY Values Min Max Mode 0 ...

Page 151

... W83C553F 6.2.3 Example Multiword DMA ATA Data Transfer Timing Table 6-8. Multiword DMA ATA Data Transfer Timing Parameter t0 Cycle Time tC IDEDAK[A:B]# to IDEDRQ[A:B] delay tD IDEIOR[A:B]# / IDEIOW[A:B]# 16-bit minimum command active time WINBOND SYSTEMS LABORATORY Values Min Max Mode 0 480ns Mode 1 150ns Mode 2 120ns Mode 3 ...

Page 152

... W83C553F Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing Parameter tE IDEIOR[A:B]# data access tF IDEIOR[A:B]# read data hold tZ IDEDAK[A:B]# to tri-state tG IDEIOR[A:B]# / IDEIOW[A:B]# data setup tH IDEIOR[A:B]# / IDEIOW[A:B]# write data hold WINBOND SYSTEMS LABORATORY Values Min Max Mode 0 150ns Mode 1 60ns Mode 2 - Mode 3 Mode 0 ...

Page 153

... W83C553F Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing Parameter tI IDEDAK[A:B]# to IDEIOR[A:B]# / IDEIOW[A:B]# setup tJ IDEIOR[A:B]# / IDEIOW[A:B]# to IDEDAK[A:B]# hold tKr IDEIOR[A:B]# negated pulse width tKw IDEIOW[A:B]# negated pulse width tLr IDEIOR[A:B]# to IDEDRQ[A:B] delay tLw IDEIOW[A:B]# to IDEDRQ[A:B] delay WINBOND SYSTEMS LABORATORY Values Min ...

Page 154

... W83C553F 6.3 ISA Bus Timing WINBOND SYSTEMS LABORATORY Table 6-9. ISA Master Write to PCI Timing Diagrams 151 ...

Page 155

... W83C553F WINBOND SYSTEMS LABORATORY Table 6-10. ISA Master Read from PCI Timing Diagrams 152 ...

Page 156

... W83C553F 7.0 MECHANICAL DESCRIPTION This chapter shows the dimensions of the W83C553F Enhanced SIO with PCI Arbiter chip. 208L QFP (28X28 mm footprint 2.6mm) 208 See Detail F Seating Plane Symbol WINBOND SYSTEMS LABORATORY 157 156 105 104 ...

Page 157

... W83C553F 8.0 Thermal Information Theta JA = Thermal Resistance between Junction and Ambient for the 208PQFP. 0 Theta JA = 43.13 C/W (air velocity = 0 M/s) 0 35.25 C/W(air velocity = 1 M/s) 0 30.90 C/W (air velocity = 2M/s) Theta junction ambient Where P = Power dissipation on the chip (in watts) chip WINBOND SYSTEMS LABORATORY ; chip Thermal Information 154 ...

Page 158

... W83C553F Driving capacity of output and input/output pins of 553F (Revision G) Pin Name A20M#/PCIRST# 22 AD[31:0] 29-31, 33-37, 41-44, 46, 47, 49, 50, 62-67, 69, 71, 73-79, 81 C/BE[3:0]# 39, 51, 61, 72 PAR 60 FRAME# 53 PERR# 58 IRDY# 54 TRDY# 55 DEVSEL# 56 STOP# 57 SERR# 59 INT[C:D]# 19, 18 GNT0#/PIBREQ# 26 GNT1#/IDEREQ# 28 ARBDIS#/GNT2# 16 PCI5TH#/GNT3# 13 GNT4#/FLSHREQ# 6 PWRPC/X86#/CPUGNT# ...

Page 159

... W83C553F IOCHRDY 135 BALE 168 AEN 136 TC 166 DAK[2:0] 194, 192, 195 PMACT#/ISARST 5 SD[15:0] 208-204, 202, 199, 197, 123, 125, 126, 128-131, 133 SECURITY/XDR# 116 XOE# 117 XCS0/ROMCS 119 XCS1/X8XCS 118 INT 10 NMI 11 INIT 3 SPKR 134 IGNNE#/HRESET# 4 Note 1: The driving capacity of these I/O cells is based on PCI specification Note 2: This is the clock output buffer ...

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