w83c553f Winbond Electronics Corp America, w83c553f Datasheet - Page 31

• Manufacturer Part Number: w83c553f
• Description: System I/o Controller With Pci Arbiter
• Manufacturer: Winbond Electronics Corp America

W83C553F
The W83C553F is a multi-function PCI device. "Function 0" is the PCI-to-ISA bridge logic; "Function 1" is the bus master
IDE controller. Each function has its own separate PCI configuration space and I/O register space.
The W83C553F's bus hierarchy is designed to provide concurrency of operations performed on all buses simultaneously and
is structured as follows:
The W83C553F accepts cycles from the PCI bus and translates them onto the ISA bus. It also requests the PCI master bridge
to generate PCI cycles on behalf of IDE DMA or an ISA master. The ISA bus interface thus contains a standard ISA Bus
Controller and data buffering logic. ISA control includes ISA command generation, I/O recovery control, wait-state
insertion, and data buffer routing. Five ISA slots can be supported without external buffering circuitry.
The W83C553F initiates and performs standard ISA bus refreshing. The integrated controller generates the command and
refresh address to the ISA bus. Since an ISA refresh is transparent to the PCI bus and the DMA cycle, an arbiter resolves any
conflicts among PCI, refresh, and DMA cycles.
IDE data transfers are executed with two specific protocols. The standard protocol is to execute PIO cycles on the PCI bus
and the dual IDE interfaces. An enhanced protocol is supported, allowing the W83C553F to transfer data across the PCI bus
as a bus master directly to/from memory, and across the dual IDE interfaces with single or multiword DMA cycles. This
protocol minimizes CPU overhead while maximizing the PCI bus bandwidth.
All IDE PIO protocol data transfers (8-bit, 16-bit and 32-bit) are automatically detected and supported. Read ahead can be
enabled for each individual device for 16-bit and 32-bit I/O read operations. This allows the controller to execute additional
IDE read cycles while the host is completing the previous memory write. Posted writes can be enabled for each individual
device for 16-bit and 32-bit I/O write operations which allow the IDE controller to complete the present write cycle while the
host executes the next system memory read operation maximizing the disk sub-system performance while reducing system
overhead.
Bus Master data/command transfers are supported as defined in the proposed PCI "Programming Interface for Bus Master IDE
Controller" specification Rev. 1.0 (SFF8038i). This allows the system microprocessor to be freed from the task of manually
transferring data between the IDE controller and the system memory as is required by the standard PIO protocol. In a
multitasking environment, the system CPU can perform other tasks with the maximum PCI bus bandwidth available while data
transfers are executed by the W83C553F.
WINBOND SYSTEMS LABORATORY
3.0 SYSTEM ARCHITECTURE
3.1
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Overview
PCI Bus is primary I/O bus
ISA Bus is secondary I/O bus
Electrical Specifications
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