w83c553f Winbond Electronics Corp America, w83c553f Datasheet - Page 99
w83c553f
Manufacturer Part Number
w83c553f
Description
System I/o Controller With Pci Arbiter
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83C553F.pdf
(159 pages)
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W83C553F
Operational Control Word 3 Register
Function:
Type:
Bit Description:
WINBOND SYSTEMS LABORATORY
Bit 7:
Bit 6:
Bit 5:
Bits [4:3]:
Bit 2:
Bits [1:0]:
The Operational Control Word 3 (OCW3) Register serves three functions. It enables special mask mode
and controls poll mode and IRR/ISR register read.
Read/Write
Reserved. This bit must be "0."
SMM. Special Mask Mode. If ESMM and SMM are both "1," the interrupt controller enters
SMM. If ESMM is "1" and SMM is "0," the interrupt controller is in normal mask mode. When
ESMM is "0," SMM has no effect.
ESMM. Enable Special Mask Mode. If ESMM is "1," the SMM bit is enabled to set or reset
Special Mask Mode. If ESMM is "0," the SMM bit is a "don't care."
OCW3SEL[1:0]. OCW3 Select. Always ensure bit 4 is "0" and bit 3 is "1" when writing an
OCW3.
POLC. When this Poll Mode Command bit is "0," the Poll Command is not issured. When this
bit is "1," the next I/O read to the interrupt controller is treated as an interrupt acknowledge
cycle.
REGREAD and ISRIRR. These Register Read Command bits provide control for reading the
In-Service Register (ISR) and Interrupt Request Register (IRR), as shown below.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function
No action
No action
Read IRQ register IRR
Read IS register ISR
Electrical Specifications
96
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