w83c553f Winbond Electronics Corp America, w83c553f Datasheet - Page 34

• Manufacturer Part Number: w83c553f
• Description: System I/o Controller With Pci Arbiter
• Manufacturer: Winbond Electronics Corp America

W83C553F
The W83C553F PCI System I/O provides the PCI bus interface functions. It contains both PCI master and slave bus
bridging. When PIBGNT# is asserted, the master bridge translates an ISA master or DMA cycle to the PCI bus, based on the
ISA Address Decoder status. When PIBGNT# is de-asserted, the slave bridge accepts these cycles, initiated from the PCI
bus, and targeted to the W83C553F's internal registers or ISA bus. The PCI Address Decoder supports the slave bridge in
processing the PCI master initiated cycles. The cycles are then forwarded to the ISA bus interface for translation onto the
ISA bus.
As a PCI slave, the W83C553F responds to both I/O and memory transactions. It always target-terminates after the first data
phase of a bursting cycle. It also converts a single interrupt acknowledge cycle into two cycles for the two internal 82C59s.
The W83C553F functions as the subtractive decoder in a PCI/ISA system by accepting all accesses not positively decoded by
some other device. This function only applies to the low 64 K I/O or low 16 M memory accesses.
The W83C553F positively decodes I/O addresses for internal registers by asserting DEVSEL# on the medium timing. In the
x86 mode, the keyboard controller and RTC are subtractively decoded.
As long as PIBGNT# is asserted, the PCI master bridge, on behalf of DMA devices or ISA Masters, drives the PCI
address/data, C/BE[3:0]# and PAR signals. When MEMR# or MEMW# is asserted, the W83C553F sends FRAME# and
IRDY# to the PCI bus if the targeted memory is not on the ISA side. Addresses and commands are valid during the address
phase, while PAR is asserted one clock later. The W83C553F always activates FRAME# for 2 PCLKs because it does not
conduct bursting cycles for PCI-to-ISA reads or writes.
The ISA Address Decoder determines the destination of the ISA master or DMA devices. It provides the following options,
as defined in Registers 48h to 4Bh:
The PCI bus cycle can be split into two phases, the address phase and the data phase. The address phase of a PCI cycle is
defined as the first rising clock edge when FRAME# is asserted. On this clock edge, C/BE[3:0]# contains the bus command
that defines the PCI bus cycle, AD [31:0] contains a valid address, and IDSEL will be stable and valid if it is a configuration
cycle. All subsequent clocks comprise the data phase until the cycle is complete. If this cycle is claimed, DEVSEL# will be
asserted.
WINBOND SYSTEMS LABORATORY
3.4
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3.5
PCI-to-ISA Bridge
PCI Bus Cycles
Memory space 0 - 512KB
Memory space 512 KB - 640 KB
Video Buffer memory space 640 KB - 768 KB
Expansion ROM memory space 768 KB - 896 KB, in eight 16 KB sections
Lower BIOS memory space 896 KB - 960 KB
Memory space within 1 MB - x MB - 16 MB. Not accessible to the PCI bus.
Memory space less than 16 MB automatically forwards to the PCI.
Electrical Specifications
31