ne56632-xx NXP Semiconductors, ne56632-xx Datasheet - Page 10

• Manufacturer Part Number: ne56632-xx
• Description: Active-low System Reset With Adjustable Delay Time
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TIMING DIAGRAM
The timing diagram in Figure 23 depicts the operation of the device.
Letters A–N on the TIME axis indicates specific events.
A: At “A”, V
increases but abruptly decreases when V
(approximately 0.65 V) that activates the internal bias circuitry and
RESET is asserted.
B: At “B”, V
delay time, t
operating level. The V
C: At “C”, V
instant, the IC releases the hold on the V
then goes HIGH (assuming the reset pull-up resistor R
connected to V
release the reset from the microprocessor, allowing the
microprocessor to function normally.
D-E: At “D”, V
continues to fall until the V
reached at “E”. This causes a reset signal to be generated (V
goes LOW).
E-F: Between “E” and “F”, V
rising.
F: At “F”, V
initiates the delay timer.
F-G: V
(t
V
2003 Oct 14
PLH
OUT
Active-LOW system reset with adjustable delay time
) times out and once again, then it releases the hold on the
reset.
CC
(RESET)
V
V
rises above V
PLH
CC
OUT
CC
CC
CC
CC
CC
CC
rises to the V
is initiated while V
begins to increase. Also the V
reaches the threshold level of V
is above V
V
V
). In a microprocessor based system these events
begins to fall, causing V
A
OUT
SH
voltage remains in a low voltage state.
SL
SL
and returns to normal. At “G”, the delay
undervoltage detection threshold is
SH
CC
and the delay time elapses. At this
B
level. Once again, the device
continues to fall and then starts
CC
t
PLH
rises above V
OUT
CC
OUT
C
reaches the level
reset. The reset output
OUT
to follow. V
SH
D E
voltage initially
. At this point the
SH
to its normal
PU
F
Figure 23. Timing diagram.
is
CC
t
OUT
PLH
G
10
H
G-H: At “G”, V
causing V
no reset signal will be generated.
H: At event “H”, V
threshold is reached. At this level, a RESET signal is generated and
V
H-I: Between “H” and “I”, V
rise rising. V
again initiated.
I-J: Between “I” and “J”, V
then falls back to V
reasserted before the delay time has elapsed. The time between “I”
and “J” is less than t
released and the reset output remains LOW.
K–L: Between “K” and “L”, V
operating level causing the reset delay to be initiated at “K” and the
reset to be released at “L”.
M: At “M”, V
Reset goes LOW).
N: At “N”, the V
circuit bias is unable to maintain a V
rise to less than 0.65 V. As V
also decreases to zero.
I
OUT
< t
PLH
goes LOW.
J
OUT
K
CC
CC
to follow it. As long as V
rises to the V
CC
falls to V
CC
t
PLH
SL
is above the upper threshold and begins to fall,
CC
PLH
voltage has decreased until normal internal
level at “J”. At “J”, the reset signal is
falls until the V
(reset delay time). Thus, the reset is not
L
SL
CC
CC
where the reset is asserted (V
CC
SH
CC
rises above V
continues to fall and then starts to
level at “I”, where the delay time is
decreases further, the V
rises again back to normal
OUT
M
SL
CC
undervoltage detection
reset. As a result, V
remains above the V
V
NE56632-XX
hys
SH
N
to V
SL01606
CC
V
V
normal and
Product data
SH
SL
OUT
OUT
CC
reset
SH
may
,